BOARD_INIT long
board_init(void)
{
at91rm9200_set_subtype(AT91_ST_RM9200_PQFP);
at91rm9200_config_uart(AT91_ID_DBGU, 0, 0); /* DBGU just Tx and Rx */
at91rm9200_config_uart(AT91RM9200_ID_USART0, 1, 0); /* Tx and Rx */
at91rm9200_config_uart(AT91RM9200_ID_USART1, 2, 0); /* Tx and Rx */
at91rm9200_config_uart(AT91RM9200_ID_USART2, 3, 0); /* Tx and Rx */
at91rm9200_config_uart(AT91RM9200_ID_USART3, 4, 0); /* Tx and Rx */
at91rm9200_config_mci(0); /* tsc4370 board has only 1 wire */
/* Newer boards may have 4 wires */
/* Configure TWI */
/* Configure SPI + dataflash */
/* Configure SSC */
/* Configure USB Host */
/* Configure FPGA attached to chip selects */
/* Pin assignment */
/* Assert PA24 low -- talk to rubidium */
at91_pio_use_gpio(AT91RM92_PIOA_BASE, AT91C_PIO_PA24);
at91_pio_gpio_output(AT91RM92_PIOA_BASE, AT91C_PIO_PA24, 0);
at91_pio_gpio_clear(AT91RM92_PIOA_BASE, AT91C_PIO_PA24);
at91_pio_use_gpio(AT91RM92_PIOB_BASE,
AT91C_PIO_PB16 | AT91C_PIO_PB17 | AT91C_PIO_PB18 | AT91C_PIO_PB19);
return (at91_ramsize());
}
static int
at91_usart_requires_rts0_workaround(struct uart_softc *sc)
{
int value;
int unit;
unit = device_get_unit(sc->sc_dev);
/*
* On the rm9200 chips, the PA21/RTS0 pin is not correctly wired to the
* usart device interally (so-called 'erratum 39', but it's 41.14 in rev
* I of the manual). This prevents use of the hardware flow control
* feature in the usart itself. It also means that if we are to
* implement RTS/CTS flow via the tty layer logic, we must use pin PA21
* as a gpio and manually manipulate it in at91_usart_bus_setsig(). We
* can only safely do so if we've been given permission via a hint,
* otherwise we might manipulate a pin that's attached to who-knows-what
* and Bad Things could happen.
*/
if (at91_is_rm92() && unit == 1) {
value = 0;
resource_int_value(device_get_name(sc->sc_dev), unit,
"use_rts0_workaround", &value);
if (value != 0) {
at91_pio_use_gpio(AT91RM92_PIOA_BASE, AT91C_PIO_PA21);
at91_pio_gpio_output(AT91RM92_PIOA_BASE,
AT91C_PIO_PA21, 1);
at91_pio_use_periph_a(AT91RM92_PIOA_BASE,
AT91C_PIO_PA20, 0);
return (1);
}
}
return (0);
}
static void
bi_nand(void)
{
/* Samsung 256MB SLC Flash */
/* Setup Static Memory Controller */
at91_smc_setup(0, 3, &nand_smc);
at91_enable_nand(&nand_param);
/*
* This assumes
* - RNB is on pin PC13
* - CE is on pin PC14
*
* Nothing actually uses RNB right now.
*
* For CE, this currently asserts it during board setup and leaves it
* that way forever.
*
* All this can go away when the gpio pin-renumbering happens...
*/
at91_pio_use_gpio(AT91SAM9260_PIOC_BASE, AT91C_PIO_PC13 | AT91C_PIO_PC14);
at91_pio_gpio_input(AT91SAM9260_PIOC_BASE, AT91C_PIO_PC13); /* RNB */
at91_pio_gpio_output(AT91SAM9260_PIOC_BASE, AT91C_PIO_PC14, 0); /* nCS */
at91_pio_gpio_clear(AT91SAM9260_PIOC_BASE, AT91C_PIO_PC14); /* Assert nCS */
}
static int
pinctrl_configure_pins(device_t bus, phandle_t cfgxref)
{
struct pinctrl_softc *sc;
struct pincfg *cfg, *cfgdata;
char name[32];
phandle_t node;
ssize_t npins;
int i;
sc = device_get_softc(bus);
node = OF_node_from_xref(cfgxref);
memset(name, 0, sizeof(name));
OF_getprop(node, "name", name, sizeof(name));
npins = OF_getencprop_alloc(node, "atmel,pins", sizeof(*cfgdata),
(void **)&cfgdata);
if (npins < 0) {
printf("We're doing it wrong %s\n", name);
return (ENXIO);
}
if (npins == 0)
return (0);
for (i = 0, cfg = cfgdata; i < npins; i++, cfg++) {
uint32_t pio;
pio = (0xfffffff & sc->ranges[0].bus) + 0x200 * cfg->unit;
printf("P%c%d %s %#x\n", cfg->unit + 'A', cfg->pin,
periphs[cfg->periph], cfg->flags);
switch (cfg->periph) {
case 0:
at91_pio_use_gpio(pio, 1u << cfg->pin);
at91_pio_gpio_pullup(pio, 1u << cfg->pin,
!!(cfg->flags & 1));
at91_pio_gpio_high_z(pio, 1u << cfg->pin,
!!(cfg->flags & 2));
at91_pio_gpio_set_deglitch(pio,
1u << cfg->pin, !!(cfg->flags & 4));
// at91_pio_gpio_pulldown(pio, 1u << cfg->pin,
// !!(cfg->flags & 8));
// at91_pio_gpio_dis_schmidt(pio,
// 1u << cfg->pin, !!(cfg->flags & 16));
break;
case 1:
at91_pio_use_periph_a(pio, 1u << cfg->pin, cfg->flags);
break;
case 2:
at91_pio_use_periph_b(pio, 1u << cfg->pin, cfg->flags);
break;
}
}
OF_prop_free(cfgdata);
return (0);
}
BOARD_INIT long
board_init(void)
{
#if 0
/* PIOB's A periph: Turn USART 0's TX/RX pins */
at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB14_DRXD, 0);
at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB15_DTXD, 1);
/* PIOB's A periph: Turn USART 0's TX/RX pins */
at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB4_TXD0, 1);
at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB5_RXD0, 0);
at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB22_DSR0, 0);
at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB23_DCD0, 0);
at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB24_DTR0, 1);
at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB25_RI0, 0);
at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB26_RTS0, 1);
at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB27_CTS0, 0);
/* PIOB's A periph: Turn USART 1's TX/RX pins */
at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB6_TXD1, 1);
at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB7_RXD1, 0);
at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB28_RTS1, 1);
at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB29_CTS1, 0);
/* TWI Two-wire Serial Data */
at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA23_TWD, 1);
at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA24_TWCK, 1);
#if 1
/*
* Turn off Clock to DataFlash, conflicts with MCI clock.
*/
at91_pio_use_gpio(AT91SAM9G20_PIOA_BASE,AT91C_PIO_PA2);
at91_pio_gpio_input(AT91SAM9G20_PIOA_BASE,AT91C_PIO_PA2);
/* Turn off chip select to DataFlash */
at91_pio_gpio_output(AT91SAM9G20_PIOC_BASE,AT91C_PIO_PC11, 0);
at91_pio_gpio_set(AT91SAM9G20_PIOC_BASE,AT91C_PIO_PC11);
at91_pio_use_gpio(AT91SAM9G20_PIOC_BASE,AT91C_PIO_PC11);
/* Multimedia Card */
at91_pio_use_periph_b(AT91SAM9G20_PIOA_BASE,AT91C_PA0_MCDB0, 1);
at91_pio_use_periph_b(AT91SAM9G20_PIOA_BASE,AT91C_PA1_MCCDB, 1);
at91_pio_use_periph_b(AT91SAM9G20_PIOA_BASE,AT91C_PA3_MCDB3, 1);
at91_pio_use_periph_b(AT91SAM9G20_PIOA_BASE,AT91C_PA4_MCDB2, 1);
at91_pio_use_periph_b(AT91SAM9G20_PIOA_BASE,AT91C_PA5_MCDB1, 1);
at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA8_MCCK, 1);
at91_pio_use_gpio(AT91SAM9G20_PIOC_BASE, AT91C_PIO_PC9);
#else
/* SPI0 to DataFlash */
at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE, AT91C_PIO_PA0, 0);
at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE, AT91C_PIO_PA1, 0);
at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE, AT91C_PIO_PA2, 0);
at91_pio_use_periph_b(AT91SAM9G20_PIOC_BASE, AT91C_PIO_PC11,0);
at91_pio_gpio_input(AT91SAM9G20_PIOA_BASE,AT91C_PIO_PA8);
at91_pio_use_gpio(AT91SAM9G20_PIOA_BASE,AT91C_PIO_PA8);
#endif
/* EMAC */
at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA12_ETX0 , 0);
at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA13_ETX1, 0);
at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA14_ERX0, 0);
at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA15_ERX1, 0);
at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA16_ETXEN, 0);
at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA17_ERXDV, 0);
at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA18_ERXER, 0);
at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA19_ETXCK, 0);
at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA20_EMDC, 0);
at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA21_EMDIO, 0);
at91_pio_use_periph_b(AT91SAM9G20_PIOA_BASE,AT91C_PA10_ETX2_0, 0);
at91_pio_use_periph_b(AT91SAM9G20_PIOA_BASE,AT91C_PA11_ETX3_0, 0);
at91_pio_use_periph_b(AT91SAM9G20_PIOA_BASE,AT91C_PA22_ETXER, 0);
at91_pio_use_periph_b(AT91SAM9G20_PIOA_BASE,AT91C_PA25_ERX2, 0);
at91_pio_use_periph_b(AT91SAM9G20_PIOA_BASE,AT91C_PA26_ERX3, 0);
at91_pio_use_periph_b(AT91SAM9G20_PIOA_BASE,AT91C_PA27_ERXCK, 0);
at91_pio_use_periph_b(AT91SAM9G20_PIOA_BASE,AT91C_PA28_ECRS, 0);
at91_pio_use_periph_b(AT91SAM9G20_PIOA_BASE,AT91C_PA29_ECOL, 0);
#endif
return (at91_ramsize());
}
static int
at91_udp_attach(device_t dev)
{
struct at91_udp_softc *sc = device_get_softc(dev);
int err;
int rid;
/* setup AT9100 USB device controller interface softc */
sc->sc_dci.sc_clocks_on = &at91_udp_clocks_on;
sc->sc_dci.sc_clocks_off = &at91_udp_clocks_off;
sc->sc_dci.sc_clocks_arg = sc;
sc->sc_dci.sc_pull_up = &at91_udp_pull_up;
sc->sc_dci.sc_pull_down = &at91_udp_pull_down;
sc->sc_dci.sc_pull_arg = sc;
/* initialise some bus fields */
sc->sc_dci.sc_bus.parent = dev;
sc->sc_dci.sc_bus.devices = sc->sc_dci.sc_devices;
sc->sc_dci.sc_bus.devices_max = AT91_MAX_DEVICES;
/* get all DMA memory */
if (usb_bus_mem_alloc_all(&sc->sc_dci.sc_bus,
USB_GET_DMA_TAG(dev), NULL)) {
return (ENOMEM);
}
callout_init_mtx(&sc->sc_vbus, &sc->sc_dci.sc_bus.bus_mtx, 0);
/*
* configure VBUS input pin, enable deglitch and enable
* interrupt :
*/
at91_pio_use_gpio(VBUS_BASE, VBUS_MASK);
at91_pio_gpio_input(VBUS_BASE, VBUS_MASK);
at91_pio_gpio_set_deglitch(VBUS_BASE, VBUS_MASK, 1);
at91_pio_gpio_set_interrupt(VBUS_BASE, VBUS_MASK, 0);
/*
* configure PULLUP output pin :
*/
at91_pio_use_gpio(PULLUP_BASE, PULLUP_MASK);
at91_pio_gpio_output(PULLUP_BASE, PULLUP_MASK, 0);
at91_udp_pull_down(sc);
/* wait 10ms for pulldown to stabilise */
usb_pause_mtx(NULL, hz / 100);
sc->sc_mclk = at91_pmc_clock_ref("mck");
sc->sc_iclk = at91_pmc_clock_ref("udc_clk");
sc->sc_fclk = at91_pmc_clock_ref("udpck");
rid = MEM_RID;
sc->sc_dci.sc_io_res =
bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
if (!(sc->sc_dci.sc_io_res)) {
err = ENOMEM;
goto error;
}
sc->sc_dci.sc_io_tag = rman_get_bustag(sc->sc_dci.sc_io_res);
sc->sc_dci.sc_io_hdl = rman_get_bushandle(sc->sc_dci.sc_io_res);
sc->sc_dci.sc_io_size = rman_get_size(sc->sc_dci.sc_io_res);
rid = 0;
sc->sc_dci.sc_irq_res =
bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE);
if (!(sc->sc_dci.sc_irq_res)) {
goto error;
}
sc->sc_dci.sc_bus.bdev = device_add_child(dev, "usbus", -1);
if (!(sc->sc_dci.sc_bus.bdev)) {
goto error;
}
device_set_ivars(sc->sc_dci.sc_bus.bdev, &sc->sc_dci.sc_bus);
err = bus_setup_intr(dev, sc->sc_dci.sc_irq_res, INTR_TYPE_TTY | INTR_MPSAFE,
at91dci_filter_interrupt, at91dci_interrupt, sc, &sc->sc_dci.sc_intr_hdl);
if (err) {
sc->sc_dci.sc_intr_hdl = NULL;
goto error;
}
err = at91dci_init(&sc->sc_dci);
if (!err) {
err = device_probe_and_attach(sc->sc_dci.sc_bus.bdev);
}
if (err) {
goto error;
} else {
/* poll VBUS one time */
USB_BUS_LOCK(&sc->sc_dci.sc_bus);
at91_vbus_poll(sc);
USB_BUS_UNLOCK(&sc->sc_dci.sc_bus);
}
return (0);
error:
at91_udp_detach(dev);
return (ENXIO);
}
BOARD_INIT long
board_init(void)
{
int is_bga, rev_mii;
/*
* Deal with bootinfo (if any) passed in from the boot2 bootloader and
* copied to the static inkernel_bootinfo earlier in the init. Do this
* early so that bootverbose is set from this point on.
*/
if (inkernel_bootinfo.bi_size > 0 &&
(inkernel_bootinfo.bi_flags & RB_BOOTINFO)) {
struct tsc_bootinfo *bip = &inkernel_bootinfo;
printf("TSC_BOOTINFO: size %u howtoflags=0x%08x rootdev='%s'\n",
bip->bi_size, bip->bi_flags, bip->bi_rootdevname);
boothowto = bip->bi_flags;
bootverbose = (boothowto & RB_VERBOSE);
if (bip->bi_rootdevname[0] != 0)
rootdevnames[0] = bip->bi_rootdevname;
}
/*
* The only way to know if we're in a BGA package (and thus have PIOD)
* is to be told via a hint; there's nothing detectable in the silicon.
* This is esentially an rm92-specific extension to getting the chip ID
* (which was done by at91_machdep just before calling this routine).
* If it is the BGA package, enable the clock for PIOD.
*/
is_bga = 0;
resource_int_value("at91", 0, "is_bga_package", &is_bga);
if (is_bga)
WR4HW(AT91RM92_PMC_BASE, PMC_PCER, 1u << AT91RM92_IRQ_PIOD);
#if __FreeBSD_version >= 1000000
at91rm9200_set_subtype(is_bga ? AT91_ST_RM9200_BGA :
AT91_ST_RM9200_PQFP);
#endif
/*
* Go reprogram the MCK frequency based on hints.
*/
master_clock_init();
/*
* Configure UARTs.
*/
at91rm9200_config_uart(AT91_ID_DBGU, 0, 0); /* DBGU just Tx and Rx */
at91rm9200_config_uart(AT91RM9200_ID_USART0, 1, 0); /* Tx and Rx */
at91rm9200_config_uart(AT91RM9200_ID_USART1, 2, 0); /* Tx and Rx */
at91rm9200_config_uart(AT91RM9200_ID_USART2, 3, 0); /* Tx and Rx */
at91rm9200_config_uart(AT91RM9200_ID_USART3, 4, 0); /* Tx and Rx */
/*
* Configure MCI (sdcard)
*/
at91rm9200_config_mci(0);
/*
* Assign the pins needed by the emac device, and power it up. Also,
* configure it for RMII operation unless the 'revmii_mode' hint is set,
* in which case configure the full set of MII pins. The revmii_mode
* hint is for so-called reverse-MII, used for connections to a Broadcom
* 5325E switch on some boards. Note that order is important here:
* configure pins, then power on the device, then access the device's
* config registers.
*/
rev_mii = 0;
resource_int_value("ate", 0, "phy_revmii_mode", &rev_mii);
at91_pio_use_periph_a(AT91RM92_PIOA_BASE,
AT91C_PIO_PA7 | AT91C_PIO_PA8 | AT91C_PIO_PA9 |
AT91C_PIO_PA10 | AT91C_PIO_PA11 | AT91C_PIO_PA12 |
AT91C_PIO_PA13 | AT91C_PIO_PA14 | AT91C_PIO_PA15 |
AT91C_PIO_PA16, 0);
if (rev_mii) {
at91_pio_use_periph_b(AT91RM92_PIOB_BASE,
AT91C_PIO_PB12 | AT91C_PIO_PB13 | AT91C_PIO_PB14 |
AT91C_PIO_PB15 | AT91C_PIO_PB16 | AT91C_PIO_PB17 |
AT91C_PIO_PB18 | AT91C_PIO_PB19, 0);
}
WR4HW(AT91RM92_PMC_BASE, PMC_PCER, 1u << AT91RM92_IRQ_EMAC);
if (!rev_mii) {
WR4HW(AT91RM92_EMAC_BASE, ETH_CFG,
RD4HW(AT91RM92_EMAC_BASE, ETH_CFG) | ETH_CFG_RMII);
}
/*
* Get our ethernet MAC address from the ID eeprom.
* Configures TWI as a side effect.
*/
set_mac_from_idprom();
/*
* Configure SPI
*/
assign_spi_pins();
/*
* Configure SSC
*/
at91_pio_use_periph_a(
AT91RM92_PIOB_BASE,
AT91C_PIO_PB6 | AT91C_PIO_PB7 | AT91C_PIO_PB8 | /* transmit */
AT91C_PIO_PB9 | AT91C_PIO_PB10 | AT91C_PIO_PB11, /* receive */
0); /* no pullup */
/*
* We're using TC1's A1 input for PPS measurements that drive the
* kernel PLL and our NTP refclock. On some old boards we route a 5mhz
* signal to TC1's A2 input (pin PA21), but we have never used that
* clock (it rolls over too fast for hz=100), and now newer boards are
* using pin PA21 as a CTS0 for USART1, so we no longer assign it to
* the timer block like we used to here.
*/
at91_pio_use_periph_b(AT91RM92_PIOA_BASE, AT91C_PIO_PA19, 0);
/*
* Configure pins used to bitbang-upload the firmware to the main FPGA.
*/
at91_pio_use_gpio(AT91RM92_PIOB_BASE,
AT91C_PIO_PB16 | AT91C_PIO_PB17 | AT91C_PIO_PB18 | AT91C_PIO_PB19);
return (at91_ramsize());
}
