static void clk_utmi_unprepare(struct clk_hw *hw) { struct clk_utmi *utmi = to_clk_utmi(hw); struct at91_pmc *pmc = utmi->pmc; u32 tmp = at91_pmc_read(AT91_CKGR_UCKR) & ~AT91_PMC_UPLLEN; pmc_write(pmc, AT91_CKGR_UCKR, tmp); }
static void inline pmc_check_mckrdy(void) { u32 r; do { r = at91_pmc_read(AT91_PMC_SR); } while (!(r & AT91_PMC_MCKRDY)); }
/* * Verify that all the clocks are correct before entering * slow-clock mode. */ static int at91_pm_verify_clocks(void) { unsigned long scsr; int i; scsr = at91_pmc_read(AT91_PMC_SCSR); /* USB must not be using PLLB */ if (cpu_is_at91rm9200()) { if ((scsr & (AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP)) != 0) { pr_err("AT91: PM - Suspend-to-RAM with USB still active\n"); return 0; } } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263() || cpu_is_at91sam9g20() || cpu_is_at91sam9g10()) { if ((scsr & (AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP)) != 0) { pr_err("AT91: PM - Suspend-to-RAM with USB still active\n"); return 0; } } if (!IS_ENABLED(CONFIG_AT91_PROGRAMMABLE_CLOCKS)) return 1; /* PCK0..PCK3 must be disabled, or configured to use clk32k */ for (i = 0; i < 4; i++) { u32 css; if ((scsr & (AT91_PMC_PCK0 << i)) == 0) continue; css = at91_pmc_read(AT91_PMC_PCKR(i)) & AT91_PMC_CSS; if (css != AT91_PMC_CSS_SLOW) { pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css); return 0; } } return 1; }
static int at91_pm_verify_clocks(void) { unsigned long scsr; int i; scsr = at91_pmc_read(AT91_PMC_SCSR); /* */ if (cpu_is_at91rm9200()) { if ((scsr & (AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP)) != 0) { pr_err("AT91: PM - Suspend-to-RAM with USB still active\n"); return 0; } } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263() || cpu_is_at91sam9g20() || cpu_is_at91sam9g10()) { if ((scsr & (AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP)) != 0) { pr_err("AT91: PM - Suspend-to-RAM with USB still active\n"); return 0; } } #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS /* */ for (i = 0; i < 4; i++) { u32 css; if ((scsr & (AT91_PMC_PCK0 << i)) == 0) continue; css = at91_pmc_read(AT91_PMC_PCKR(i)) & AT91_PMC_CSS; if (css != AT91_PMC_CSS_SLOW) { pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css); return 0; } } #endif return 1; }
static int clk_utmi_prepare(struct clk_hw *hw) { struct clk_utmi *utmi = to_clk_utmi(hw); struct at91_pmc *pmc = utmi->pmc; u32 tmp = at91_pmc_read(AT91_CKGR_UCKR) | AT91_PMC_UPLLEN | AT91_PMC_UPLLCOUNT | AT91_PMC_BIASEN; pmc_write(pmc, AT91_CKGR_UCKR, tmp); while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_LOCKU)) { enable_irq(utmi->irq); wait_event(utmi->wait, pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_LOCKU); } return 0; }
static int at91_pm_enter(suspend_state_t state) { if (of_have_populated_dt()) at91_pinctrl_gpio_suspend(); else at91_gpio_suspend(); at91_irq_suspend(); pr_debug("AT91: PM - wake mask %08x, pm state %d\n", /* remember all the always-wake irqs */ (at91_pmc_read(AT91_PMC_PCSR) | (1 << AT91_ID_FIQ) | (1 << AT91_ID_SYS) | (at91_get_extern_irq())) & at91_aic_read(AT91_AIC_IMR), state); switch (state) { /* * Suspend-to-RAM is like STANDBY plus slow clock mode, so * drivers must suspend more deeply: only the master clock * controller may be using the main oscillator. */ case PM_SUSPEND_MEM: /* * Ensure that clocks are in a valid state. */ if (!at91_pm_verify_clocks()) goto error; /* * Enter slow clock mode by switching over to clk32k and * turning off the main oscillator; reverse on wakeup. */ if (slow_clock) { int memctrl = AT91_MEMCTRL_SDRAMC; if (cpu_is_at91rm9200()) memctrl = AT91_MEMCTRL_MC; else if (cpu_is_at91sam9g45()) memctrl = AT91_MEMCTRL_DDRSDR; #ifdef CONFIG_AT91_SLOW_CLOCK /* copy slow_clock handler to SRAM, and call it */ memcpy(slow_clock, at91_slow_clock, at91_slow_clock_sz); #endif slow_clock(at91_pmc_base, at91_ramc_base[0], at91_ramc_base[1], memctrl); break; } else { pr_info("AT91: PM - no slow clock mode enabled ...\n"); /* FALLTHROUGH leaving master clock alone */ } /* * STANDBY mode has *all* drivers suspended; ignores irqs not * marked as 'wakeup' event sources; and reduces DRAM power. * But otherwise it's identical to PM_SUSPEND_ON: cpu idle, and * nothing fancy done with main or cpu clocks. */ case PM_SUSPEND_STANDBY: /* * NOTE: the Wait-for-Interrupt instruction needs to be * in icache so no SDRAM accesses are needed until the * wakeup IRQ occurs and self-refresh is terminated. * For ARM 926 based chips, this requirement is weaker * as at91sam9 can access a RAM in self-refresh mode. */ if (at91_pm_standby) at91_pm_standby(); break; case PM_SUSPEND_ON: cpu_do_idle(); break; default: pr_debug("AT91: PM - bogus suspend state %d\n", state); goto error; } pr_debug("AT91: PM - wakeup %08x\n", at91_aic_read(AT91_AIC_IPR) & at91_aic_read(AT91_AIC_IMR)); error: target_state = PM_SUSPEND_ON; at91_irq_resume(); if (of_have_populated_dt()) at91_pinctrl_gpio_resume(); else at91_gpio_resume(); return 0; }
void __bare_init at91sam926x_lowlevel_init(struct at91sam926x_lowlevel_cfg *cfg) { u32 r; int in_sram = running_in_sram(); at91sam926x_lowlevel_board_config(cfg); __raw_writel(cfg->wdt_mr, AT91_BASE_WDT + AT91_WDT_MR); /* configure PIOx as EBI0 D[16-31] */ at91_mux_gpio_disable(cfg->pio, cfg->ebi_pio_pdr); at91_mux_set_pullup(cfg->pio, cfg->ebi_pio_ppudr, true); if (cfg->ebi_pio_is_peripha) at91_mux_set_A_periph(cfg->pio, cfg->ebi_pio_ppudr); at91_sys_write(cfg->matrix_csa, cfg->ebi_csa); /* flash */ at91_smc_write(cfg->smc_cs, AT91_SAM9_SMC_MODE, cfg->smc_mode); at91_smc_write(cfg->smc_cs, AT91_SMC_CYCLE, cfg->smc_cycle); at91_smc_write(cfg->smc_cs, AT91_SMC_PULSE, cfg->smc_pulse); at91_smc_write(cfg->smc_cs, AT91_SMC_SETUP, cfg->smc_setup); /* * PMC Check if the PLL is already initialized */ r = at91_pmc_read(AT91_PMC_MCKR); if (r & AT91_PMC_CSS && !in_sram) return; /* * Enable the Main Oscillator */ at91_pmc_write(AT91_CKGR_MOR, cfg->pmc_mor); do { r = at91_pmc_read(AT91_PMC_SR); } while (!(r & AT91_PMC_MOSCS)); /* * PLLAR: x MHz for PCK */ at91_pmc_write(AT91_CKGR_PLLAR, cfg->pmc_pllar); do { r = at91_pmc_read(AT91_PMC_SR); } while (!(r & AT91_PMC_LOCKA)); /* * PCK/x = MCK Master Clock from SLOW */ at91_pmc_write(AT91_PMC_MCKR, cfg->pmc_mckr1); pmc_check_mckrdy(); /* * PCK/x = MCK Master Clock from PLLA */ at91_pmc_write(AT91_PMC_MCKR, cfg->pmc_mckr2); pmc_check_mckrdy(); /* * Init SDRAM */ at91sam926x_sdramc_init(cfg); /* User reset enable*/ at91_sys_write(AT91_RSTC_MR, cfg->rstc_rmr); #ifdef CONFIG_SYS_MATRIX_MCFG_REMAP /* MATRIX_MCFG - REMAP all masters */ at91_sys_write(AT91_MATRIX_MCFG0, 0x1FF); #endif /* * When boot from external boot * we need to enable mck and ohter clock * so enable all of them * We will shutdown what we don't need later */ at91_pmc_write(AT91_PMC_PCER, 0xffffffff); }
static int at91_pm_enter(suspend_state_t state) { at91_gpio_suspend(); at91_irq_suspend(); pr_debug("AT91: PM - wake mask %08x, pm state %d\n", /* */ (at91_pmc_read(AT91_PMC_PCSR) | (1 << AT91_ID_FIQ) | (1 << AT91_ID_SYS) | (at91_extern_irq)) & at91_aic_read(AT91_AIC_IMR), state); switch (state) { /* */ case PM_SUSPEND_MEM: /* */ if (!at91_pm_verify_clocks()) goto error; /* */ if (slow_clock) { int memctrl = AT91_MEMCTRL_SDRAMC; if (cpu_is_at91rm9200()) memctrl = AT91_MEMCTRL_MC; else if (cpu_is_at91sam9g45()) memctrl = AT91_MEMCTRL_DDRSDR; #ifdef CONFIG_AT91_SLOW_CLOCK /* */ memcpy(slow_clock, at91_slow_clock, at91_slow_clock_sz); #endif slow_clock(at91_pmc_base, at91_ramc_base[0], at91_ramc_base[1], memctrl); break; } else { pr_info("AT91: PM - no slow clock mode enabled ...\n"); /* */ } /* */ case PM_SUSPEND_STANDBY: /* */ at91_standby(); break; case PM_SUSPEND_ON: cpu_do_idle(); break; default: pr_debug("AT91: PM - bogus suspend state %d\n", state); goto error; } pr_debug("AT91: PM - wakeup %08x\n", at91_aic_read(AT91_AIC_IPR) & at91_aic_read(AT91_AIC_IMR)); error: target_state = PM_SUSPEND_ON; at91_irq_resume(); at91_gpio_resume(); return 0; }