static void at91sam9n12ek_nand_hw_init(void)
{
struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
unsigned long csa;
/* Assign CS3 to NAND/SmartMedia Interface */
csa = readl(&matrix->ebicsa);
csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
/* Configure databus */
csa &= ~AT91_MATRIX_NFD0_ON_D16; /* nandflash connect to D0~D15 */
/* Configure IO drive */
csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
writel(csa, &matrix->ebicsa);
/* Configure SMC CS3 for NAND/SmartMedia */
writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
&smc->cs[3].setup);
writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
&smc->cs[3].pulse);
writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(7),
&smc->cs[3].cycle);
writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
AT91_SMC_MODE_EXNW_DISABLE |
#ifdef CONFIG_SYS_NAND_DBW_16
AT91_SMC_MODE_DBW_16 |
#else /* CONFIG_SYS_NAND_DBW_8 */
AT91_SMC_MODE_DBW_8 |
#endif
AT91_SMC_MODE_TDF_CYCLE(1),
&smc->cs[3].mode);
/* Configure RDY/BSY pin */
at91_set_pio_input(AT91_PIO_PORTD, 5, 1);
/* Configure ENABLE pin for NandFlash */
at91_set_pio_output(AT91_PIO_PORTD, 4, 1);
at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
at91_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* ALE */
at91_set_a_periph(AT91_PIO_PORTD, 3, 1); /* CLE */
}
void vinco_macb0_hw_init(void)
{
at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */
at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */
at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */
at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */
at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */
at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */
at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */
at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */
at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */
at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_GMAC0);
/* Enable Phy*/
at91_set_pio_output(AT91_PIO_PORTE, 8, 1);
}
static void pm9g45_nand_hw_init(void)
{
unsigned long csa;
at91_smc_t *smc = (at91_smc_t *) AT91_SMC_BASE;
at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE;
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
/* Enable CS3 */
csa = readl(&matrix->ccr[6]) | AT91_MATRIX_CSA_EBI_CS3A;
writel(csa, &matrix->ccr[6]);
/* Configure SMC CS3 for NAND/SmartMedia */
writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
&smc->cs[3].setup);
writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) |
AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2),
&smc->cs[3].pulse);
writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4),
&smc->cs[3].cycle);
writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
AT91_SMC_MODE_EXNW_DISABLE |
AT91_SMC_MODE_DBW_8 |
AT91_SMC_MODE_TDF_CYCLE(3),
&smc->cs[3].mode);
writel(1 << AT91SAM9G45_ID_PIOC, &pmc->pcer);
#ifdef CONFIG_SYS_NAND_READY_PIN
/* Configure RDY/BSY */
at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
#endif
/* Enable NandFlash */
at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
}
int checkboard(void)
{
char str[32];
u_char hw_type; /* hardware type */
/* read the "Type" register of the ET1100 controller */
hw_type = readb(CONFIG_ET1100_BASE);
switch (hw_type) {
case 0x11:
case 0x3F:
/* ET1100 present, arch number of MEESC-Board */
gd->bd->bi_arch_number = MACH_TYPE_MEESC;
puts("Board: CAN-EtherCAT Gateway");
break;
case 0xFF:
/* no ET1100 present, arch number of EtherCAN/2-Board */
gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2;
puts("Board: EtherCAN/2 Gateway");
/* switch on LED1D */
at91_set_pio_output(AT91_PIO_PORTB, 12, 1);
break;
default:
/* assume, no ET1100 present, arch number of EtherCAN/2-Board */
gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2;
printf("ERROR! Read invalid hw_type: %02X\n", hw_type);
puts("Board: EtherCAN/2 Gateway");
break;
}
if (getenv_f("serial#", str, sizeof(str)) > 0) {
puts(", serial# ");
puts(str);
}
printf("\nHardware-revision: 1.%d\n", get_hw_rev());
printf("Mach-type: %lu\n", gd->bd->bi_arch_number);
return 0;
}
void at91_ohci_hw_init(void)
{
at91_set_pio_output(AT91_PIO_PORTB, 7, 0);
}
void lcd_disable(void)
{
at91_set_pio_output(AT91_PIO_PORTC, 25, 1); /* power down */
}
void lcd_enable(void)
{
at91_set_pio_output(AT91_PIO_PORTC, 25, 0); /* power up */
}
static void board_usb_hw_init(void)
{
at91_set_pio_output(AT91_PIO_PORTB, 10, 1);
}
void spi_cs_deactivate(struct spi_slave *slave)
{
at91_set_pio_output(AT91_PIO_PORTC, 3, 1);
}
int gpio_direction_output(unsigned gpio, int value)
{
at91_set_pio_output(at91_gpio_to_port(gpio),
at91_gpio_to_pin(gpio), value);
return 0;
}
static void ma5d4evk_usb_hw_init(void)
{
at91_set_pio_output(AT91_PIO_PORTE, 11, 0);
at91_set_pio_output(AT91_PIO_PORTE, 14, 0);
}
void at91sam9n12ek_usb_hw_init(void)
{
at91_set_pio_output(AT91_PIO_PORTB, 7, 0);
}
static void sama5d3xek_mci_hw_init(void)
{
at91_mci_hw_init();
at91_set_pio_output(AT91_PIO_PORTB, 10, 0); /* MCI0 Power */
}
static void sama5d3xek_usb_hw_init(void)
{
at91_set_pio_output(AT91_PIO_PORTD, 25, 0);
at91_set_pio_output(AT91_PIO_PORTD, 26, 0);
at91_set_pio_output(AT91_PIO_PORTD, 27, 0);
}
static void sama5d4_xplained_usb_hw_init(void)
{
at91_set_pio_output(AT91_PIO_PORTE, 11, 1);
at91_set_pio_output(AT91_PIO_PORTE, 14, 1);
}
void at91_uhp_hw_init(void)
{
/* Enable VBus on UHP ports */
at91_set_pio_output(AT91_PIO_PORTA, 21, 0);
at91_set_pio_output(AT91_PIO_PORTA, 24, 0);
}
void spi_cs_deactivate(struct spi_slave *slave)
{
debug("spi_cs_deactivate: bus=%u cs=%u\n", slave->bus, slave->cs);
at91_set_pio_output(cs_to_portbit[slave->bus][slave->cs].port,
cs_to_portbit[slave->bus][slave->cs].bit, 1);
}
static void sama5d3_xplained_usb_hw_init(void)
{
at91_set_pio_output(AT91_PIO_PORTE, 3, 0);
at91_set_pio_output(AT91_PIO_PORTE, 4, 0);
}
static void sama5d3_xplained_mci0_hw_init(void)
{
at91_set_pio_output(AT91_PIO_PORTE, 2, 0); /* MCI0 Power */
}
static void vinco_usb_hw_init(void)
{
at91_set_pio_output(AT91_PIO_PORTE, 11, 0);
at91_set_pio_output(AT91_PIO_PORTE, 12, 0);
at91_set_pio_output(AT91_PIO_PORTE, 10, 0);
}
void spi_cs_activate(struct spi_slave *slave)
{
at91_set_pio_output(AT91_PIO_PORTA, 17, 0);
}