static int ns87415_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) { static const struct ata_port_info info = { .flags = ATA_FLAG_SLAVE_POSS, .pio_mask = ATA_PIO4, .mwdma_mask = ATA_MWDMA2, .port_ops = &ns87415_pata_ops, }; const struct ata_port_info *ppi[] = { &info, NULL }; int rc; #if defined(CONFIG_SUPERIO) static const struct ata_port_info info87560 = { .flags = ATA_FLAG_SLAVE_POSS, .pio_mask = ATA_PIO4, .mwdma_mask = ATA_MWDMA2, .port_ops = &ns87560_pata_ops, }; if (PCI_SLOT(pdev->devfn) == 0x0E) ppi[0] = &info87560; #endif ata_print_version_once(&pdev->dev, DRV_VERSION); rc = pcim_enable_device(pdev); if (rc) return rc; ns87415_fixup(pdev); return ata_pci_bmdma_init_one(pdev, ppi, &ns87415_sht, NULL, 0); }
static int optidma_init_one(struct pci_dev *dev, const struct pci_device_id *id) { static const struct ata_port_info info_82c700 = { .flags = ATA_FLAG_SLAVE_POSS, .pio_mask = ATA_PIO4, .mwdma_mask = ATA_MWDMA2, .port_ops = &optidma_port_ops }; static const struct ata_port_info info_82c700_udma = { .flags = ATA_FLAG_SLAVE_POSS, .pio_mask = ATA_PIO4, .mwdma_mask = ATA_MWDMA2, .udma_mask = ATA_UDMA2, .port_ops = &optiplus_port_ops }; const struct ata_port_info *ppi[] = { &info_82c700, NULL }; int rc; ata_print_version_once(&dev->dev, DRV_VERSION); rc = pcim_enable_device(dev); if (rc) return rc; inw(0x1F1); inw(0x1F1); pci_clock = inb(0x1F5) & 1; if (optiplus_with_udma(dev)) ppi[0] = &info_82c700_udma; return ata_pci_bmdma_init_one(dev, ppi, &optidma_sht, NULL, 0); }
static int netcell_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) { static const struct ata_port_info info = { .flags = ATA_FLAG_SLAVE_POSS, /* Actually we don't really care about these as the firmware deals with it */ .pio_mask = ATA_PIO4, .mwdma_mask = ATA_MWDMA2, .udma_mask = ATA_UDMA5, /* UDMA 133 */ .port_ops = &netcell_ops, }; const struct ata_port_info *port_info[] = { &info, NULL }; int rc; ata_print_version_once(&pdev->dev, DRV_VERSION); rc = pcim_enable_device(pdev); if (rc) return rc; /* Any chip specific setup/optimisation/messages here */ ata_pci_bmdma_clear_simplex(pdev); /* And let the library code do the work */ return ata_pci_bmdma_init_one(pdev, port_info, &netcell_sht, NULL, 0); }
static int netcell_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) { static const struct ata_port_info info = { .flags = ATA_FLAG_SLAVE_POSS, /* */ .pio_mask = ATA_PIO4, .mwdma_mask = ATA_MWDMA2, .udma_mask = ATA_UDMA5, /* */ .port_ops = &netcell_ops, }; const struct ata_port_info *port_info[] = { &info, NULL }; int rc; ata_print_version_once(&pdev->dev, DRV_VERSION); rc = pcim_enable_device(pdev); if (rc) return rc; /* */ ata_pci_bmdma_clear_simplex(pdev); /* */ return ata_pci_bmdma_init_one(pdev, port_info, &netcell_sht, NULL, 0); }
static int artop_init_one (struct pci_dev *pdev, const struct pci_device_id *id) { static const struct ata_port_info info_6210 = { .flags = ATA_FLAG_SLAVE_POSS, .pio_mask = ATA_PIO4, .mwdma_mask = ATA_MWDMA2, .udma_mask = ATA_UDMA2, .port_ops = &artop6210_ops, }; static const struct ata_port_info info_626x = { .flags = ATA_FLAG_SLAVE_POSS, .pio_mask = ATA_PIO4, .mwdma_mask = ATA_MWDMA2, .udma_mask = ATA_UDMA4, .port_ops = &artop6260_ops, }; static const struct ata_port_info info_628x = { .flags = ATA_FLAG_SLAVE_POSS, .pio_mask = ATA_PIO4, .mwdma_mask = ATA_MWDMA2, .udma_mask = ATA_UDMA5, .port_ops = &artop6260_ops, }; static const struct ata_port_info info_628x_fast = { .flags = ATA_FLAG_SLAVE_POSS, .pio_mask = ATA_PIO4, .mwdma_mask = ATA_MWDMA2, .udma_mask = ATA_UDMA6, .port_ops = &artop6260_ops, }; const struct ata_port_info *ppi[] = { NULL, NULL }; int rc; ata_print_version_once(&pdev->dev, DRV_VERSION); rc = pcim_enable_device(pdev); if (rc) return rc; if (id->driver_data == 0) /* 6210 variant */ ppi[0] = &info_6210; else if (id->driver_data == 1) /* 6260 */ ppi[0] = &info_626x; else if (id->driver_data == 2) { /* 6280 or 6280 + fast */ unsigned long io = pci_resource_start(pdev, 4); ppi[0] = &info_628x; if (inb(io) & 0x10) ppi[0] = &info_628x_fast; } BUG_ON(ppi[0] == NULL); atp8xx_fixup(pdev); return ata_pci_bmdma_init_one(pdev, ppi, &artop_sht, NULL, 0); }
static int opti_init_one(struct pci_dev *dev, const struct pci_device_id *id) { static const struct ata_port_info info = { .flags = ATA_FLAG_SLAVE_POSS, .pio_mask = ATA_PIO4, .port_ops = &opti_port_ops }; const struct ata_port_info *ppi[] = { &info, NULL }; ata_print_version_once(&dev->dev, DRV_VERSION); return ata_pci_sff_init_one(dev, ppi, &opti_sht, NULL, 0); }
static int radisys_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) { static const struct ata_port_info info = { .flags = ATA_FLAG_SLAVE_POSS, .pio_mask = ATA_PIO4, .mwdma_mask = ATA_MWDMA12_ONLY, .udma_mask = ATA_UDMA24_ONLY, .port_ops = &radisys_pata_ops, }; const struct ata_port_info *ppi[] = { &info, NULL }; ata_print_version_once(&pdev->dev, DRV_VERSION); return ata_pci_bmdma_init_one(pdev, ppi, &radisys_sht, NULL, 0); }
static int atp867x_init_one(struct pci_dev *pdev, const struct pci_device_id *id) { static const struct ata_port_info info_867x = { .flags = ATA_FLAG_SLAVE_POSS, .pio_mask = ATA_PIO4, .udma_mask = ATA_UDMA6, .port_ops = &atp867x_ops, }; struct ata_host *host; const struct ata_port_info *ppi[] = { &info_867x, NULL }; int rc; ata_print_version_once(&pdev->dev, DRV_VERSION); rc = pcim_enable_device(pdev); if (rc) return rc; printk(KERN_INFO "ATP867X: ATP867 ATA UDMA133 controller (rev %02X)", pdev->device); host = ata_host_alloc_pinfo(&pdev->dev, ppi, ATP867X_NUM_PORTS); if (!host) { dev_err(&pdev->dev, "failed to allocate ATA host\n"); rc = -ENOMEM; goto err_out; } rc = atp867x_ata_pci_sff_init_host(host); if (rc) { dev_err(&pdev->dev, "failed to init host\n"); goto err_out; } pci_set_master(pdev); rc = ata_host_activate(host, pdev->irq, ata_bmdma_interrupt, IRQF_SHARED, &atp867x_sht); if (rc) dev_err(&pdev->dev, "failed to activate host\n"); err_out: return rc; }
static int sil680_init_one(struct pci_dev *pdev, const struct pci_device_id *id) { static const struct ata_port_info info = { .flags = ATA_FLAG_SLAVE_POSS, .pio_mask = ATA_PIO4, .mwdma_mask = ATA_MWDMA2, .udma_mask = ATA_UDMA6, .port_ops = &sil680_port_ops }; static const struct ata_port_info info_slow = { .flags = ATA_FLAG_SLAVE_POSS, .pio_mask = ATA_PIO4, .mwdma_mask = ATA_MWDMA2, .udma_mask = ATA_UDMA5, .port_ops = &sil680_port_ops }; const struct ata_port_info *ppi[] = { &info, NULL }; struct ata_host *host; void __iomem *mmio_base; int rc, try_mmio; ata_print_version_once(&pdev->dev, DRV_VERSION); rc = pcim_enable_device(pdev); if (rc) return rc; switch (sil680_init_chip(pdev, &try_mmio)) { case 0: ppi[0] = &info_slow; break; case 0x30: return -ENODEV; } if (!try_mmio) goto use_ioports; /* Try to acquire MMIO resources and fallback to PIO if * that fails */ rc = pcim_iomap_regions(pdev, 1 << SIL680_MMIO_BAR, DRV_NAME); if (rc) goto use_ioports; /* Allocate host and set it up */ host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2); if (!host) return -ENOMEM; host->iomap = pcim_iomap_table(pdev); /* Setup DMA masks */ rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); if (rc) return rc; rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); if (rc) return rc; pci_set_master(pdev); /* Get MMIO base and initialize port addresses */ mmio_base = host->iomap[SIL680_MMIO_BAR]; host->ports[0]->ioaddr.bmdma_addr = mmio_base + 0x00; host->ports[0]->ioaddr.cmd_addr = mmio_base + 0x80; host->ports[0]->ioaddr.ctl_addr = mmio_base + 0x8a; host->ports[0]->ioaddr.altstatus_addr = mmio_base + 0x8a; ata_sff_std_ports(&host->ports[0]->ioaddr); host->ports[1]->ioaddr.bmdma_addr = mmio_base + 0x08; host->ports[1]->ioaddr.cmd_addr = mmio_base + 0xc0; host->ports[1]->ioaddr.ctl_addr = mmio_base + 0xca; host->ports[1]->ioaddr.altstatus_addr = mmio_base + 0xca; ata_sff_std_ports(&host->ports[1]->ioaddr); /* Register & activate */ return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt, IRQF_SHARED, &sil680_sht); use_ioports: return ata_pci_bmdma_init_one(pdev, ppi, &sil680_sht, NULL, 0); }
static int sis_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) { struct ata_port_info pi = sis_port_info; const struct ata_port_info *ppi[] = { &pi, &pi }; struct ata_host *host; u32 genctl, val; u8 pmr; u8 port2_start = 0x20; int i, rc; ata_print_version_once(&pdev->dev, DRV_VERSION); rc = pcim_enable_device(pdev); if (rc) return rc; /* check and see if the SCRs are in IO space or PCI cfg space */ pci_read_config_dword(pdev, SIS_GENCTL, &genctl); if ((genctl & GENCTL_IOMAPPED_SCR) == 0) pi.flags |= SIS_FLAG_CFGSCR; /* if hardware thinks SCRs are in IO space, but there are * no IO resources assigned, change to PCI cfg space. */ if ((!(pi.flags & SIS_FLAG_CFGSCR)) && ((pci_resource_start(pdev, SIS_SCR_PCI_BAR) == 0) || (pci_resource_len(pdev, SIS_SCR_PCI_BAR) < 128))) { genctl &= ~GENCTL_IOMAPPED_SCR; pci_write_config_dword(pdev, SIS_GENCTL, genctl); pi.flags |= SIS_FLAG_CFGSCR; } pci_read_config_byte(pdev, SIS_PMR, &pmr); switch (ent->device) { case 0x0180: case 0x0181: /* The PATA-handling is provided by pata_sis */ switch (pmr & 0x30) { case 0x10: ppi[1] = &sis_info133_for_sata; break; case 0x30: ppi[0] = &sis_info133_for_sata; break; } if ((pmr & SIS_PMR_COMBINED) == 0) { dev_info(&pdev->dev, "Detected SiS 180/181/964 chipset in SATA mode\n"); port2_start = 64; } else { dev_info(&pdev->dev, "Detected SiS 180/181 chipset in combined mode\n"); port2_start = 0; pi.flags |= ATA_FLAG_SLAVE_POSS; } break; case 0x0182: case 0x0183: pci_read_config_dword(pdev, 0x6C, &val); if (val & (1L << 31)) { dev_info(&pdev->dev, "Detected SiS 182/965 chipset\n"); pi.flags |= ATA_FLAG_SLAVE_POSS; } else { dev_info(&pdev->dev, "Detected SiS 182/965L chipset\n"); } break; case 0x1182: dev_info(&pdev->dev, "Detected SiS 1182/966/680 SATA controller\n"); pi.flags |= ATA_FLAG_SLAVE_POSS; break; case 0x1183: dev_info(&pdev->dev, "Detected SiS 1183/966/966L/968/680 controller in PATA mode\n"); ppi[0] = &sis_info133_for_sata; ppi[1] = &sis_info133_for_sata; break; } rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host); if (rc) return rc; for (i = 0; i < 2; i++) { struct ata_port *ap = host->ports[i]; if (ap->flags & ATA_FLAG_SATA && ap->flags & ATA_FLAG_SLAVE_POSS) { rc = ata_slave_link_init(ap); if (rc) return rc; } } if (!(pi.flags & SIS_FLAG_CFGSCR)) { void __iomem *mmio; rc = pcim_iomap_regions(pdev, 1 << SIS_SCR_PCI_BAR, DRV_NAME); if (rc) return rc; mmio = host->iomap[SIS_SCR_PCI_BAR]; host->ports[0]->ioaddr.scr_addr = mmio; host->ports[1]->ioaddr.scr_addr = mmio + port2_start; } pci_set_master(pdev); pci_intx(pdev, 1); return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt, IRQF_SHARED, &sis_sht); }
static int hpt3x3_init_one(struct pci_dev *pdev, const struct pci_device_id *id) { static const struct ata_port_info info = { .flags = ATA_FLAG_SLAVE_POSS, .pio_mask = ATA_PIO4, #if defined(CONFIG_PATA_HPT3X3_DMA) /* Further debug needed */ .mwdma_mask = ATA_MWDMA2, .udma_mask = ATA_UDMA2, #endif .port_ops = &hpt3x3_port_ops }; /* Register offsets of taskfiles in BAR4 area */ static const u8 offset_cmd[2] = { 0x20, 0x28 }; static const u8 offset_ctl[2] = { 0x36, 0x3E }; const struct ata_port_info *ppi[] = { &info, NULL }; struct ata_host *host; int i, rc; void __iomem *base; hpt3x3_init_chipset(pdev); ata_print_version_once(&pdev->dev, DRV_VERSION); host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2); if (!host) return -ENOMEM; /* acquire resources and fill host */ rc = pcim_enable_device(pdev); if (rc) return rc; /* Everything is relative to BAR4 if we set up this way */ rc = pcim_iomap_regions(pdev, 1 << 4, DRV_NAME); if (rc == -EBUSY) pcim_pin_device(pdev); if (rc) return rc; host->iomap = pcim_iomap_table(pdev); rc = dma_set_mask(&pdev->dev, ATA_DMA_MASK); if (rc) return rc; rc = dma_set_coherent_mask(&pdev->dev, ATA_DMA_MASK); if (rc) return rc; base = host->iomap[4]; /* Bus mastering base */ for (i = 0; i < host->n_ports; i++) { struct ata_port *ap = host->ports[i]; struct ata_ioports *ioaddr = &ap->ioaddr; ioaddr->cmd_addr = base + offset_cmd[i]; ioaddr->altstatus_addr = ioaddr->ctl_addr = base + offset_ctl[i]; ioaddr->scr_addr = NULL; ata_sff_std_ports(ioaddr); ioaddr->bmdma_addr = base + 8 * i; ata_port_pbar_desc(ap, 4, -1, "ioport"); ata_port_pbar_desc(ap, 4, offset_cmd[i], "cmd"); } pci_set_master(pdev); return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt, IRQF_SHARED, &hpt3x3_sht); }