static void
aststrategy(struct buf *bp)
{
struct ast_softc *stp = bp->b_dev->si_drv1;
int s;
if (stp->device->flags & ATA_D_DETACHING) {
bp->b_flags |= B_ERROR;
bp->b_error = ENXIO;
biodone(bp);
return;
}
/* if it's a null transfer, return immediatly. */
if (bp->b_bcount == 0) {
bp->b_resid = 0;
biodone(bp);
return;
}
if (!(bp->b_flags & B_READ) && stp->flags & F_WRITEPROTECT) {
bp->b_flags |= B_ERROR;
bp->b_error = EPERM;
biodone(bp);
return;
}
/* check for != blocksize requests */
if (bp->b_bcount % stp->blksize) {
ata_prtdev(stp->device, "transfers must be multiple of %d\n",
stp->blksize);
bp->b_flags |= B_ERROR;
bp->b_error = EIO;
biodone(bp);
return;
}
/* warn about transfers bigger than the device suggests */
if (bp->b_bcount > stp->blksize * stp->cap.ctl) {
if ((stp->flags & F_CTL_WARN) == 0) {
ata_prtdev(stp->device, "WARNING: CTL exceeded %ld>%d\n",
bp->b_bcount, stp->blksize * stp->cap.ctl);
stp->flags |= F_CTL_WARN;
}
}
s = splbio();
bufq_insert_tail(&stp->queue, bp);
splx(s);
ata_start(stp->device->channel);
}
static void
ast_describe(struct ast_softc *stp)
{
if (bootverbose) {
ata_prtdev(stp->device, "<%.40s/%.8s> tape drive at ata%d as %s\n",
stp->device->param->model, stp->device->param->revision,
device_get_unit(stp->device->channel->dev),
(stp->device->unit == ATA_MASTER) ? "master" : "slave");
ata_prtdev(stp->device, "%dKB/s, ", stp->cap.max_speed);
printf("transfer limit %d blk%s, ",
stp->cap.ctl, (stp->cap.ctl > 1) ? "s" : "");
printf("%dKB buffer, ", (stp->cap.buffer_size * DEV_BSIZE) / 1024);
printf("%s\n", ata_mode2str(stp->device->mode));
ata_prtdev(stp->device, "Medium: ");
switch (stp->cap.medium_type) {
case 0x00:
printf("none"); break;
case 0x17:
printf("Travan 1 (400 Mbyte)"); break;
case 0xb6:
printf("Travan 4 (4 Gbyte)"); break;
case 0xda:
printf("OnStream ADR (15Gyte)"); break;
default:
printf("unknown (0x%x)", stp->cap.medium_type);
}
if (stp->cap.readonly) printf(", readonly");
if (stp->cap.reverse) printf(", reverse");
if (stp->cap.eformat) printf(", eformat");
if (stp->cap.qfa) printf(", qfa");
if (stp->cap.lock) printf(", lock");
if (stp->cap.locked) printf(", locked");
if (stp->cap.prevent) printf(", prevent");
if (stp->cap.eject) printf(", eject");
if (stp->cap.disconnect) printf(", disconnect");
if (stp->cap.ecc) printf(", ecc");
if (stp->cap.compress) printf(", compress");
if (stp->cap.blk512) printf(", 512b");
if (stp->cap.blk1024) printf(", 1024b");
if (stp->cap.blk32k) printf(", 32kb");
printf("\n");
}
else {
ata_prtdev(stp->device, "TAPE <%.40s> at ata%d-%s %s\n",
stp->device->param->model,
device_get_unit(stp->device->channel->dev),
(stp->device->unit == ATA_MASTER) ? "master" : "slave",
ata_mode2str(stp->device->mode));
}
}
static int
astclose(dev_t dev, int flags, int fmt, struct proc *p)
{
struct ast_softc *stp = dev->si_drv1;
/* flush buffers, some drives fail here, they should report ctl = 0 */
if (stp->cap.ctl && (stp->flags & F_DATA_WRITTEN))
ast_write_filemark(stp, 0);
/* write filemark if data written to tape */
if (!(stp->flags & F_ONSTREAM) &&
(stp->flags & (F_DATA_WRITTEN | F_FM_WRITTEN)) == F_DATA_WRITTEN)
ast_write_filemark(stp, WF_WRITE);
/* if minor is even rewind on close */
if (!(minor(dev) & 0x01))
ast_rewind(stp);
if (stp->cap.lock && count_dev(dev) == 1)
ast_prevent_allow(stp, 0);
stp->flags &= F_CTL_WARN;
#ifdef AST_DEBUG
ata_prtdev(stp->device, "%llu total bytes transferred\n", ast_total);
#endif
return 0;
}
static int
ata_getparam(struct ata_device *atadev, u_int8_t command)
{
struct ata_params *ata_parm;
int retry = 0;
if (!(ata_parm = malloc(sizeof(struct ata_params), M_ATA, M_NOWAIT))) {
ata_prtdev(atadev, "malloc for identify data failed\n");
return -1;
}
/* apparently some devices needs this repeated */
do {
if (ata_command(atadev, command, 0, 0, 0, ATA_IMMEDIATE)) {
ata_prtdev(atadev, "%s identify failed\n",
command == ATA_C_ATAPI_IDENTIFY ? "ATAPI" : "ATA");
free(ata_parm, M_ATA);
return -1;
}
if (retry++ > 4) {
ata_prtdev(atadev, "%s identify retries exceeded\n",
command == ATA_C_ATAPI_IDENTIFY ? "ATAPI" : "ATA");
free(ata_parm, M_ATA);
return -1;
}
} while (ata_wait(atadev, ((command == ATA_C_ATAPI_IDENTIFY) ?
ATA_S_DRQ : (ATA_S_READY|ATA_S_DSC|ATA_S_DRQ))));
ATA_INSW(atadev->channel->r_io, ATA_DATA, (int16_t *)ata_parm,
sizeof(struct ata_params)/sizeof(int16_t));
if (command == ATA_C_ATA_IDENTIFY ||
!((ata_parm->model[0] == 'N' && ata_parm->model[1] == 'E') ||
(ata_parm->model[0] == 'F' && ata_parm->model[1] == 'X') ||
(ata_parm->model[0] == 'P' && ata_parm->model[1] == 'i')))
bswap(ata_parm->model, sizeof(ata_parm->model));
btrim(ata_parm->model, sizeof(ata_parm->model));
bpack(ata_parm->model, ata_parm->model, sizeof(ata_parm->model));
bswap(ata_parm->revision, sizeof(ata_parm->revision));
btrim(ata_parm->revision, sizeof(ata_parm->revision));
bpack(ata_parm->revision, ata_parm->revision, sizeof(ata_parm->revision));
bswap(ata_parm->serial, sizeof(ata_parm->serial));
btrim(ata_parm->serial, sizeof(ata_parm->serial));
bpack(ata_parm->serial, ata_parm->serial, sizeof(ata_parm->serial));
atadev->param = ata_parm;
return 0;
}
int
astattach(struct ata_device *atadev)
{
struct ast_softc *stp;
struct ast_readposition position;
dev_t dev;
stp = malloc(sizeof(struct ast_softc), M_AST, M_NOWAIT | M_ZERO);
if (!stp) {
ata_prtdev(atadev, "out of memory\n");
return 0;
}
stp->device = atadev;
stp->lun = ata_get_lun(&ast_lun_map);
ata_set_name(atadev, "ast", stp->lun);
bufq_init(&stp->queue);
if (ast_sense(stp)) {
free(stp, M_AST);
return 0;
}
if (!strcmp(atadev->param->model, "OnStream DI-30")) {
struct ast_transferpage transfer;
struct ast_identifypage identify;
stp->flags |= F_ONSTREAM;
bzero(&transfer, sizeof(struct ast_transferpage));
ast_mode_sense(stp, ATAPI_TAPE_TRANSFER_PAGE,
&transfer, sizeof(transfer));
bzero(&identify, sizeof(struct ast_identifypage));
ast_mode_sense(stp, ATAPI_TAPE_IDENTIFY_PAGE,
&identify, sizeof(identify));
strncpy(identify.ident, "FBSD", 4);
ast_mode_select(stp, &identify, sizeof(identify));
ast_read_position(stp, 0, &position);
}
devstat_add_entry(&stp->stats, "ast", stp->lun, DEV_BSIZE,
DEVSTAT_NO_ORDERED_TAGS,
DEVSTAT_TYPE_SEQUENTIAL | DEVSTAT_TYPE_IF_IDE,
DEVSTAT_PRIORITY_TAPE);
dev = make_dev(&ast_cdevsw, dkmakeminor(stp->lun, 0, 0),
UID_ROOT, GID_OPERATOR, 0640, "ast%d", stp->lun);
dev->si_drv1 = stp;
dev->si_iosize_max = 256 * DEV_BSIZE;
stp->dev1 = dev;
dev = make_dev(&ast_cdevsw, dkmakeminor(stp->lun, 0, 1),
UID_ROOT, GID_OPERATOR, 0640, "nast%d", stp->lun);
dev->si_drv1 = stp;
dev->si_iosize_max = 256 * DEV_BSIZE;
stp->dev2 = dev;
stp->device->flags |= ATA_D_MEDIA_CHANGED;
ast_describe(stp);
atadev->driver = stp;
return 1;
}
int
ata_wait(struct ata_device *atadev, u_int8_t mask)
{
int timeout = 0;
DELAY(1);
while (timeout < 5000000) { /* timeout 5 secs */
atadev->channel->status = ATA_INB(atadev->channel->r_io, ATA_STATUS);
/* if drive fails status, reselect the drive just to be sure */
if (atadev->channel->status == 0xff) {
ata_prtdev(atadev, "no status, reselecting device\n");
ATA_OUTB(atadev->channel->r_io, ATA_DRIVE, ATA_D_IBM|atadev->unit);
DELAY(10);
atadev->channel->status = ATA_INB(atadev->channel->r_io,ATA_STATUS);
if (atadev->channel->status == 0xff)
return -1;
}
/* are we done ? */
if (!(atadev->channel->status & ATA_S_BUSY))
break;
if (timeout > 1000) {
timeout += 1000;
DELAY(1000);
}
else {
timeout += 10;
DELAY(10);
}
}
if (atadev->channel->status & ATA_S_ERROR)
atadev->channel->error = ATA_INB(atadev->channel->r_io, ATA_ERROR);
if (timeout >= 5000000)
return -1;
if (!mask)
return (atadev->channel->status & ATA_S_ERROR);
/* Wait 50 msec for bits wanted. */
timeout = 5000;
while (timeout--) {
atadev->channel->status = ATA_INB(atadev->channel->r_io, ATA_STATUS);
if ((atadev->channel->status & mask) == mask) {
if (atadev->channel->status & ATA_S_ERROR)
atadev->channel->error=ATA_INB(atadev->channel->r_io,ATA_ERROR);
return (atadev->channel->status & ATA_S_ERROR);
}
DELAY (10);
}
return -1;
}
static int
ata_wait(struct ata_device *atadev, u_int8_t mask)
{
u_int8_t status;
int timeout = 0;
DELAY(1);
/* wait 5 seconds for device to get !BUSY */
while (timeout < 5000000) {
status = ATA_IDX_INB(atadev->channel, ATA_STATUS);
/* if drive fails status, reselect the drive just to be sure */
if (status == 0xff) {
ata_prtdev(atadev, "WARNING no status, reselecting device\n");
ATA_IDX_OUTB(atadev->channel, ATA_DRIVE, ATA_D_IBM | atadev->unit);
DELAY(10);
status = ATA_IDX_INB(atadev->channel, ATA_STATUS);
if (status == 0xff)
return -1;
}
/* are we done ? */
if (!(status & ATA_S_BUSY))
break;
if (timeout > 1000) {
timeout += 1000;
DELAY(1000);
}
else {
timeout += 10;
DELAY(10);
}
}
if (timeout >= 5000000)
return -1;
if (!mask)
return (status & ATA_S_ERROR);
DELAY(1);
/* wait 50 msec for bits wanted */
timeout = 5000;
while (timeout--) {
status = ATA_IDX_INB(atadev->channel, ATA_STATUS);
if ((status & mask) == mask)
return (status & ATA_S_ERROR);
DELAY (10);
}
return -1;
}
int
afdattach(struct ata_device *atadev)
{
struct afd_softc *fdp;
dev_t dev;
fdp = malloc(sizeof(struct afd_softc), M_AFD, M_NOWAIT | M_ZERO);
if (!fdp) {
ata_prtdev(atadev, "out of memory\n");
return 0;
}
fdp->device = atadev;
fdp->lun = ata_get_lun(&afd_lun_map);
ata_set_name(atadev, "afd", fdp->lun);
bufq_init(&fdp->queue);
if (afd_sense(fdp)) {
free(fdp, M_AFD);
return 0;
}
devstat_add_entry(&fdp->stats, "afd", fdp->lun, DEV_BSIZE,
DEVSTAT_NO_ORDERED_TAGS,
DEVSTAT_TYPE_DIRECT | DEVSTAT_TYPE_IF_IDE,
DEVSTAT_PRIORITY_WFD);
dev = disk_create(fdp->lun, &fdp->disk, 0, &afd_cdevsw, &afddisk_cdevsw);
dev->si_drv1 = fdp;
fdp->dev = dev;
if (!strncmp(atadev->param->model, "IOMEGA ZIP", 10) ||
!strncmp(atadev->param->model, "IOMEGA Clik!", 12))
fdp->dev->si_iosize_max = 64 * DEV_BSIZE;
else
fdp->dev->si_iosize_max = 252 * DEV_BSIZE;
afd_describe(fdp);
atadev->flags |= ATA_D_MEDIA_CHANGED;
atadev->driver = fdp;
return 1;
}
static int
astopen(dev_t dev, int flags, int fmt, struct proc *p)
{
struct ast_softc *stp = dev->si_drv1;
if (!stp)
return ENXIO;
if (count_dev(dev) > 1)
return EBUSY;
atapi_test_ready(stp->device);
if (stp->cap.lock)
ast_prevent_allow(stp, 1);
if (ast_sense(stp))
ata_prtdev(stp->device, "sense media type failed\n");
stp->device->flags &= ~ATA_D_MEDIA_CHANGED;
stp->flags &= ~(F_DATA_WRITTEN | F_FM_WRITTEN);
ast_total = 0;
return 0;
}
int
ata_command(struct ata_device *atadev, u_int8_t command,
u_int64_t lba, u_int16_t count, u_int8_t feature, int flags)
{
int error = 0;
#ifdef ATA_DEBUG
ata_prtdev(atadev, "ata_command: addr=%04lx, cmd=%02x, "
"lba=%lld, count=%d, feature=%d, flags=%02x\n",
rman_get_start(atadev->channel->r_io),
command, lba, count, feature, flags);
#endif
/* select device */
ATA_OUTB(atadev->channel->r_io, ATA_DRIVE, ATA_D_IBM | atadev->unit);
/* disable interrupt from device */
if (atadev->channel->flags & ATA_QUEUED)
ATA_OUTB(atadev->channel->r_altio, ATA_ALTSTAT, ATA_A_IDS | ATA_A_4BIT);
/* ready to issue command ? */
if (ata_wait(atadev, 0) < 0) {
ata_prtdev(atadev, "timeout sending command=%02x s=%02x e=%02x\n",
command, atadev->channel->status, atadev->channel->error);
return -1;
}
/* only use 48bit addressing if needed because of the overhead */
if ((lba >= 268435455 || count > 256) && atadev->param &&
atadev->param->support.address48) {
ATA_OUTB(atadev->channel->r_io, ATA_FEATURE, (feature>>8) & 0xff);
ATA_OUTB(atadev->channel->r_io, ATA_FEATURE, feature);
ATA_OUTB(atadev->channel->r_io, ATA_COUNT, (count>>8) & 0xff);
ATA_OUTB(atadev->channel->r_io, ATA_COUNT, count & 0xff);
ATA_OUTB(atadev->channel->r_io, ATA_SECTOR, (lba>>24) & 0xff);
ATA_OUTB(atadev->channel->r_io, ATA_SECTOR, lba & 0xff);
ATA_OUTB(atadev->channel->r_io, ATA_CYL_LSB, (lba>>32) & 0xff);
ATA_OUTB(atadev->channel->r_io, ATA_CYL_LSB, (lba>>8) & 0xff);
ATA_OUTB(atadev->channel->r_io, ATA_CYL_MSB, (lba>>40) & 0xff);
ATA_OUTB(atadev->channel->r_io, ATA_CYL_MSB, (lba>>16) & 0xff);
ATA_OUTB(atadev->channel->r_io, ATA_DRIVE, ATA_D_LBA | atadev->unit);
/* translate command into 48bit version */
switch (command) {
case ATA_C_READ:
command = ATA_C_READ48; break;
case ATA_C_READ_MUL:
command = ATA_C_READ_MUL48; break;
case ATA_C_READ_DMA:
command = ATA_C_READ_DMA48; break;
case ATA_C_READ_DMA_QUEUED:
command = ATA_C_READ_DMA_QUEUED48; break;
case ATA_C_WRITE:
command = ATA_C_WRITE48; break;
case ATA_C_WRITE_MUL:
command = ATA_C_WRITE_MUL48; break;
case ATA_C_WRITE_DMA:
command = ATA_C_WRITE_DMA48; break;
case ATA_C_WRITE_DMA_QUEUED:
command = ATA_C_WRITE_DMA_QUEUED48; break;
case ATA_C_FLUSHCACHE:
command = ATA_C_FLUSHCACHE48; break;
default:
ata_prtdev(atadev, "can't translate cmd to 48bit version\n");
return -1;
}
}
static int
ata_command(struct ata_device *atadev, u_int8_t command,
u_int64_t lba, u_int16_t count, u_int16_t feature)
{
if (atadebug)
ata_prtdev(atadev, "ata_command: addr=%04lx, command=%02x, "
"lba=%jd, count=%d, feature=%d\n",
rman_get_start(atadev->channel->r_io[ATA_DATA].res),
command, (intmax_t)lba, count, feature);
/* select device */
ATA_IDX_OUTB(atadev->channel, ATA_DRIVE, ATA_D_IBM | atadev->unit);
/* ready to issue command ? */
if (ata_wait(atadev, 0) < 0) {
ata_prtdev(atadev, "timeout sending command=%02x\n", command);
return -1;
}
/* enable interrupt */
ATA_IDX_OUTB(atadev->channel, ATA_ALTSTAT, ATA_A_4BIT);
/* only use 48bit addressing if needed (avoid bugs and overhead) */
if ((lba > 268435455 || count > 256) && atadev->param &&
atadev->param->support.command2 & ATA_SUPPORT_ADDRESS48) {
/* translate command into 48bit version */
switch (command) {
case ATA_READ:
command = ATA_READ48; break;
case ATA_READ_MUL:
command = ATA_READ_MUL48; break;
case ATA_READ_DMA:
command = ATA_READ_DMA48; break;
case ATA_READ_DMA_QUEUED:
command = ATA_READ_DMA_QUEUED48; break;
case ATA_WRITE:
command = ATA_WRITE48; break;
case ATA_WRITE_MUL:
command = ATA_WRITE_MUL48; break;
case ATA_WRITE_DMA:
command = ATA_WRITE_DMA48; break;
case ATA_WRITE_DMA_QUEUED:
command = ATA_WRITE_DMA_QUEUED48; break;
case ATA_FLUSHCACHE:
command = ATA_FLUSHCACHE48; break;
default:
ata_prtdev(atadev, "can't translate cmd to 48bit version\n");
return -1;
}
ATA_IDX_OUTB(atadev->channel, ATA_FEATURE, (feature>>8) & 0xff);
ATA_IDX_OUTB(atadev->channel, ATA_FEATURE, feature & 0xff);
ATA_IDX_OUTB(atadev->channel, ATA_COUNT, (count>>8) & 0xff);
ATA_IDX_OUTB(atadev->channel, ATA_COUNT, count & 0xff);
ATA_IDX_OUTB(atadev->channel, ATA_SECTOR, (lba>>24) & 0xff);
ATA_IDX_OUTB(atadev->channel, ATA_SECTOR, lba & 0xff);
ATA_IDX_OUTB(atadev->channel, ATA_CYL_LSB, (lba>>32) & 0xff);
ATA_IDX_OUTB(atadev->channel, ATA_CYL_LSB, (lba>>8) & 0xff);
ATA_IDX_OUTB(atadev->channel, ATA_CYL_MSB, (lba>>40) & 0xff);
ATA_IDX_OUTB(atadev->channel, ATA_CYL_MSB, (lba>>16) & 0xff);
ATA_IDX_OUTB(atadev->channel, ATA_DRIVE, ATA_D_LBA | atadev->unit);
atadev->channel->flags |= ATA_48BIT_ACTIVE;
}
else {
/* must be called with ATA channel locked */
static int
ata_transaction(struct ata_request *request)
{
/* safety check, device might have been detached FIXME SOS */
if (!request->device->param) {
request->result = ENXIO;
return ATA_OP_FINISHED;
}
/* record the request as running */
request->device->channel->running = request;
ATA_DEBUG_RQ(request, "transaction");
/* disable ATAPI DMA writes if HW doesn't support it */
if ((request->device->channel->flags & ATA_ATAPI_DMA_RO) &&
((request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)) ==
(ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)))
request->flags &= ~ATA_R_DMA;
switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA)) {
/* ATA PIO data transfer and control commands */
default:
{
/* record command direction here as our request might be gone later */
int write = (request->flags & ATA_R_WRITE);
/* issue command */
if (ata_command(request->device, request->u.ata.command,
request->u.ata.lba, request->u.ata.count,
request->u.ata.feature)) {
ata_prtdev(request->device, "error issueing PIO command\n");
request->result = EIO;
break;
}
/* if write command output the data */
if (write) {
if (ata_wait(request->device,
(ATA_S_READY | ATA_S_DSC | ATA_S_DRQ)) < 0) {
ata_prtdev(request->device,"timeout waiting for write DRQ");
request->result = EIO;
break;
}
ata_pio_write(request, request->transfersize);
}
}
/* return and wait for interrupt */
return ATA_OP_CONTINUES;
/* ATA DMA data transfer commands */
case ATA_R_DMA:
/* check sanity, setup SG list and DMA engine */
if (request->device->channel->dma->load(request->device,
request->data,
request->bytecount,
request->flags & ATA_R_READ)) {
ata_prtdev(request->device, "setting up DMA failed\n");
request->result = EIO;
break;
}
/* issue command */
if (ata_command(request->device, request->u.ata.command,
request->u.ata.lba, request->u.ata.count,
request->u.ata.feature)) {
ata_prtdev(request->device, "error issuing DMA command\n");
request->result = EIO;
break;
}
/* start DMA engine */
if (request->device->channel->dma->start(request->device->channel)) {
ata_prtdev(request->device, "error starting DMA\n");
request->result = EIO;
break;
}
/* return and wait for interrupt */
return ATA_OP_CONTINUES;
/* ATAPI PIO commands */
case ATA_R_ATAPI:
/* is this just a POLL DSC command ? */
if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) {
ATA_IDX_OUTB(request->device->channel, ATA_DRIVE,
ATA_D_IBM | request->device->unit);
DELAY(10);
if (!(ATA_IDX_INB(request->device->channel, ATA_ALTSTAT)&ATA_S_DSC))
request->result = EBUSY;
break;
}
/* start ATAPI operation */
if (ata_command(request->device, ATA_PACKET_CMD,
request->transfersize << 8, 0, 0)) {
ata_prtdev(request->device, "error issuing ATA PACKET command\n");
request->result = EIO;
break;
}
/* command interrupt device ? just return and wait for interrupt */
if ((request->device->param->config & ATA_DRQ_MASK) == ATA_DRQ_INTR)
return ATA_OP_CONTINUES;
/* wait for ready to write ATAPI command block */
{
int timeout = 5000; /* might be less for fast devices */
while (timeout--) {
int reason = ATA_IDX_INB(request->device->channel, ATA_IREASON);
int status = ATA_IDX_INB(request->device->channel, ATA_STATUS);
if (((reason & (ATA_I_CMD | ATA_I_IN)) |
(status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT)
break;
DELAY(20);
}
if (timeout <= 0) {
ata_prtdev(request->device,
"timeout waiting for ATAPI ready\n");
request->result = EIO;
break;
}
}
/* this seems to be needed for some (slow) devices */
DELAY(10);
/* output actual command block */
ATA_IDX_OUTSW_STRM(request->device->channel, ATA_DATA,
(int16_t *)request->u.atapi.ccb,
(request->device->param->config & ATA_PROTO_MASK) ==
ATA_PROTO_ATAPI_12 ? 6 : 8);
/* return and wait for interrupt */
return ATA_OP_CONTINUES;
case ATA_R_ATAPI|ATA_R_DMA:
/* is this just a POLL DSC command ? */
if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) {
ATA_IDX_OUTB(request->device->channel, ATA_DRIVE,
ATA_D_IBM | request->device->unit);
DELAY(10);
if (!(ATA_IDX_INB(request->device->channel, ATA_ALTSTAT)&ATA_S_DSC))
request->result = EBUSY;
break;
}
/* check sanity, setup SG list and DMA engine */
if (request->device->channel->dma->load(request->device,
request->data,
request->bytecount,
request->flags & ATA_R_READ)) {
ata_prtdev(request->device, "setting up DMA failed\n");
request->result = EIO;
break;
}
/* start ATAPI operation */
if (ata_command(request->device, ATA_PACKET_CMD, 0, 0, ATA_F_DMA)) {
ata_prtdev(request->device, "error issuing ATAPI packet command\n");
request->result = EIO;
break;
}
/* wait for ready to write ATAPI command block */
{
int timeout = 5000; /* might be less for fast devices */
while (timeout--) {
int reason = ATA_IDX_INB(request->device->channel, ATA_IREASON);
int status = ATA_IDX_INB(request->device->channel, ATA_STATUS);
if (((reason & (ATA_I_CMD | ATA_I_IN)) |
(status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT)
break;
DELAY(20);
}
if (timeout <= 0) {
ata_prtdev(request->device,"timeout waiting for ATAPI ready\n");
request->result = EIO;
break;
}
}
/* this seems to be needed for some (slow) devices */
DELAY(10);
/* output actual command block */
ATA_IDX_OUTSW_STRM(request->device->channel, ATA_DATA,
(int16_t *)request->u.atapi.ccb,
(request->device->param->config & ATA_PROTO_MASK) ==
ATA_PROTO_ATAPI_12 ? 6 : 8);
/* start DMA engine */
if (request->device->channel->dma->start(request->device->channel)) {
request->result = EIO;
break;
}
/* return and wait for interrupt */
return ATA_OP_CONTINUES;
}
/* request finish here */
if (request->device->channel->dma->flags & ATA_DMA_ACTIVE)
request->device->channel->dma->unload(request->device->channel);
request->device->channel->running = NULL;
return ATA_OP_FINISHED;
}
static void
ata_interrupt(void *data)
{
struct ata_channel *ch = (struct ata_channel *)data;
struct ata_request *request = ch->running;
int length;
/* ignore this interrupt if there is no running request */
if (!request) {
if (ATA_LOCK_CH(ch, ATA_CONTROL)) {
u_int8_t status = ATA_IDX_INB(ch, ATA_STATUS);
u_int8_t error = ATA_IDX_INB(ch, ATA_ERROR);
if (bootverbose)
ata_printf(ch, -1,
"spurious interrupt - status=0x%02x error=0x%02x\n",
status, error);
ATA_UNLOCK_CH(ch);
}
else {
if (bootverbose)
ata_printf(ch, -1, "spurious interrupt - channel busy\n");
}
return;
}
ATA_DEBUG_RQ(request, "interrupt");
/* ignore interrupt if device is busy */
if (!(request->flags & ATA_R_TIMEOUT) &&
ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) {
DELAY(100);
if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DRQ))
return;
}
ATA_DEBUG_RQ(request, "interrupt accepted");
/* clear interrupt and get status */
request->status = ATA_IDX_INB(ch, ATA_STATUS);
request->flags |= ATA_R_INTR_SEEN;
switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_CONTROL)) {
/* ATA PIO data transfer and control commands */
default:
/* on control commands read back registers to the request struct */
if (request->flags & ATA_R_CONTROL) {
request->u.ata.count = ATA_IDX_INB(ch, ATA_COUNT);
request->u.ata.lba = ATA_IDX_INB(ch, ATA_SECTOR) |
(ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) |
(ATA_IDX_INB(ch, ATA_CYL_MSB) << 16);
}
/* if we got an error we are done with the HW */
if (request->status & ATA_S_ERROR) {
request->error = ATA_IDX_INB(ch, ATA_ERROR);
break;
}
/* are we moving data ? */
if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
/* if read data get it */
if (request->flags & ATA_R_READ)
ata_pio_read(request, request->transfersize);
/* update how far we've gotten */
request->donecount += request->transfersize;
/* do we need a scoop more ? */
if (request->bytecount > request->donecount) {
/* set this transfer size according to HW capabilities */
request->transfersize =
min((request->bytecount - request->donecount),
request->transfersize);
/* clear interrupt seen flag as we need to wait again */
request->flags &= ~ATA_R_INTR_SEEN;
/* if data write command, output the data */
if (request->flags & ATA_R_WRITE) {
/* if we get an error here we are done with the HW */
if (ata_wait(request->device,
(ATA_S_READY | ATA_S_DSC | ATA_S_DRQ)) < 0) {
ata_prtdev(request->device,
"timeout waiting for write DRQ");
request->status = ATA_IDX_INB(ch, ATA_STATUS);
break;
}
/* output data and return waiting for new interrupt */
ata_pio_write(request, request->transfersize);
return;
}
/* if data read command, return & wait for interrupt */
if (request->flags & ATA_R_READ)
return;
}
}
/* done with HW */
break;
/* ATA DMA data transfer commands */
case ATA_R_DMA:
/* stop DMA engine and get status */
request->dmastat = ch->dma->stop(ch);
/* did we get error or data */
if (request->status & ATA_S_ERROR)
request->error = ATA_IDX_INB(ch, ATA_ERROR);
else if (request->dmastat & ATA_BMSTAT_ERROR)
request->status |= ATA_S_ERROR;
else
request->donecount = request->bytecount;
/* release SG list etc */
ch->dma->unload(ch);
/* done with HW */
break;
/* ATAPI PIO commands */
case ATA_R_ATAPI:
length = ATA_IDX_INB(ch, ATA_CYL_LSB)|(ATA_IDX_INB(ch, ATA_CYL_MSB)<<8);
switch ((ATA_IDX_INB(ch, ATA_IREASON) & (ATA_I_CMD | ATA_I_IN)) |
(request->status & ATA_S_DRQ)) {
case ATAPI_P_CMDOUT:
/* this seems to be needed for some (slow) devices */
DELAY(10);
if (!(request->status & ATA_S_DRQ)) {
ata_prtdev(request->device, "command interrupt without DRQ\n");
request->status = ATA_S_ERROR;
break;
}
ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb,
(request->device->param->config &
ATA_PROTO_MASK)== ATA_PROTO_ATAPI_12 ? 6 : 8);
/* return wait for interrupt */
return;
case ATAPI_P_WRITE:
if (request->flags & ATA_R_READ) {
request->status = ATA_S_ERROR;
ata_prtdev(request->device,
"%s trying to write on read buffer\n",
ata_cmd2str(request));
break;
}
ata_pio_write(request, length);
request->donecount += length;
/* set next transfer size according to HW capabilities */
request->transfersize = min((request->bytecount-request->donecount),
request->transfersize);
/* return wait for interrupt */
return;
case ATAPI_P_READ:
if (request->flags & ATA_R_WRITE) {
request->status = ATA_S_ERROR;
ata_prtdev(request->device,
"%s trying to read on write buffer\n",
ata_cmd2str(request));
break;
}
ata_pio_read(request, length);
request->donecount += length;
/* set next transfer size according to HW capabilities */
request->transfersize = min((request->bytecount-request->donecount),
request->transfersize);
/* return wait for interrupt */
return;
case ATAPI_P_DONEDRQ:
ata_prtdev(request->device,
"WARNING - %s DONEDRQ non conformant device\n",
ata_cmd2str(request));
if (request->flags & ATA_R_READ) {
ata_pio_read(request, length);
request->donecount += length;
}
else if (request->flags & ATA_R_WRITE) {
ata_pio_write(request, length);
request->donecount += length;
}
else
request->status = ATA_S_ERROR;
/* FALLTHROUGH */
case ATAPI_P_ABORT:
case ATAPI_P_DONE:
if (request->status & (ATA_S_ERROR | ATA_S_DWF))
request->error = ATA_IDX_INB(ch, ATA_ERROR);
break;
default:
ata_prtdev(request->device, "unknown transfer phase\n");
request->status = ATA_S_ERROR;
}
/* done with HW */
break;
/* ATAPI DMA commands */
case ATA_R_ATAPI|ATA_R_DMA:
/* stop the engine and get engine status */
request->dmastat = ch->dma->stop(ch);
/* did we get error or data */
if (request->status & (ATA_S_ERROR | ATA_S_DWF))
request->error = ATA_IDX_INB(ch, ATA_ERROR);
else if (request->dmastat & ATA_BMSTAT_ERROR)
request->status |= ATA_S_ERROR;
else
request->donecount = request->bytecount;
/* release SG list etc */
ch->dma->unload(ch);
/* done with HW */
break;
}
/* if we timed out the unlocking of the ATA channel is done later */
if (!(request->flags & ATA_R_TIMEOUT)) {
ch->running = NULL;
ATA_UNLOCK_CH(ch);
ch->locking(ch, ATA_LF_UNLOCK);
}
/* schedule completition for this request */
ata_finish(request);
}
static int
ata_end_transaction(struct ata_request *request)
{
struct ata_channel *ch = request->device->channel;
int length;
ATA_DEBUG_RQ(request, "end transaction");
/* clear interrupt and get status */
request->status = ATA_IDX_INB(ch, ATA_STATUS);
switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_CONTROL)) {
/* ATA PIO data transfer and control commands */
default:
/* XXX Doesn't handle the non-PIO case. */
if (request->flags & ATA_R_TIMEOUT)
return ATA_OP_FINISHED;
/* on control commands read back registers to the request struct */
if (request->flags & ATA_R_CONTROL) {
request->u.ata.count = ATA_IDX_INB(ch, ATA_COUNT);
request->u.ata.lba = ATA_IDX_INB(ch, ATA_SECTOR) |
(ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) |
(ATA_IDX_INB(ch, ATA_CYL_MSB) << 16) |
((ATA_IDX_INB(ch, ATA_DRIVE) & 0x0f) << 24);
}
/* if we got an error we are done with the HW */
if (request->status & ATA_S_ERROR) {
request->error = ATA_IDX_INB(ch, ATA_ERROR);
return ATA_OP_FINISHED;
}
/* are we moving data ? */
if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
/* if read data get it */
if (request->flags & ATA_R_READ)
ata_pio_read(request, request->transfersize);
/* update how far we've gotten */
request->donecount += request->transfersize;
/* do we need a scoop more ? */
if (request->bytecount > request->donecount) {
/* set this transfer size according to HW capabilities */
request->transfersize =
min((request->bytecount - request->donecount),
request->transfersize);
/* clear interrupt seen flag as we need to wait again */
request->flags &= ~ATA_R_INTR_SEEN;
/* if data write command, output the data */
if (request->flags & ATA_R_WRITE) {
/* if we get an error here we are done with the HW */
if (ata_wait(request->device,
(ATA_S_READY | ATA_S_DSC | ATA_S_DRQ)) < 0) {
ata_prtdev(request->device,
"timeout waiting for write DRQ");
request->status = ATA_IDX_INB(ch, ATA_STATUS);
return ATA_OP_FINISHED;
}
/* output data and return waiting for new interrupt */
ata_pio_write(request, request->transfersize);
return ATA_OP_CONTINUES;
}
/* if data read command, return & wait for interrupt */
if (request->flags & ATA_R_READ)
return ATA_OP_CONTINUES;
}
}
/* done with HW */
return ATA_OP_FINISHED;
/* ATA DMA data transfer commands */
case ATA_R_DMA:
/* stop DMA engine and get status */
if (ch->dma->stop)
request->dmastat = ch->dma->stop(ch);
/* did we get error or data */
if (request->status & ATA_S_ERROR)
request->error = ATA_IDX_INB(ch, ATA_ERROR);
else if (request->dmastat & ATA_BMSTAT_ERROR)
request->status |= ATA_S_ERROR;
else
request->donecount = request->bytecount;
/* release SG list etc */
ch->dma->unload(ch);
/* done with HW */
return ATA_OP_FINISHED;
/* ATAPI PIO commands */
case ATA_R_ATAPI:
length = ATA_IDX_INB(ch, ATA_CYL_LSB)|(ATA_IDX_INB(ch, ATA_CYL_MSB)<<8);
switch ((ATA_IDX_INB(ch, ATA_IREASON) & (ATA_I_CMD | ATA_I_IN)) |
(request->status & ATA_S_DRQ)) {
case ATAPI_P_CMDOUT:
/* this seems to be needed for some (slow) devices */
DELAY(10);
if (!(request->status & ATA_S_DRQ)) {
ata_prtdev(request->device, "command interrupt without DRQ\n");
request->status = ATA_S_ERROR;
return ATA_OP_FINISHED;
}
ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb,
(request->device->param->config &
ATA_PROTO_MASK)== ATA_PROTO_ATAPI_12 ? 6 : 8);
/* return wait for interrupt */
return ATA_OP_CONTINUES;
case ATAPI_P_WRITE:
if (request->flags & ATA_R_READ) {
request->status = ATA_S_ERROR;
ata_prtdev(request->device,
"%s trying to write on read buffer\n",
ata_cmd2str(request));
return ATA_OP_FINISHED;
}
ata_pio_write(request, length);
request->donecount += length;
/* set next transfer size according to HW capabilities */
request->transfersize = min((request->bytecount-request->donecount),
request->transfersize);
/* return wait for interrupt */
return ATA_OP_CONTINUES;
case ATAPI_P_READ:
if (request->flags & ATA_R_WRITE) {
request->status = ATA_S_ERROR;
ata_prtdev(request->device,
"%s trying to read on write buffer\n",
ata_cmd2str(request));
return ATA_OP_FINISHED;
}
ata_pio_read(request, length);
request->donecount += length;
/* set next transfer size according to HW capabilities */
request->transfersize = min((request->bytecount-request->donecount),
request->transfersize);
/* return wait for interrupt */
return ATA_OP_CONTINUES;
case ATAPI_P_DONEDRQ:
ata_prtdev(request->device,
"WARNING - %s DONEDRQ non conformant device\n",
ata_cmd2str(request));
if (request->flags & ATA_R_READ) {
ata_pio_read(request, length);
request->donecount += length;
}
else if (request->flags & ATA_R_WRITE) {
ata_pio_write(request, length);
request->donecount += length;
}
else
request->status = ATA_S_ERROR;
/* FALLTHROUGH */
case ATAPI_P_ABORT:
case ATAPI_P_DONE:
if (request->status & (ATA_S_ERROR | ATA_S_DWF))
request->error = ATA_IDX_INB(ch, ATA_ERROR);
return ATA_OP_FINISHED;
default:
ata_prtdev(request->device, "unknown transfer phase\n");
request->status = ATA_S_ERROR;
}
/* done with HW */
return ATA_OP_FINISHED;
/* ATAPI DMA commands */
case ATA_R_ATAPI|ATA_R_DMA:
/* stop the engine and get engine status */
if (ch->dma->stop)
request->dmastat = ch->dma->stop(ch);
/* did we get error or data */
if (request->status & (ATA_S_ERROR | ATA_S_DWF))
request->error = ATA_IDX_INB(ch, ATA_ERROR);
else if (request->dmastat & ATA_BMSTAT_ERROR)
request->status |= ATA_S_ERROR;
else
request->donecount = request->bytecount;
/* release SG list etc */
ch->dma->unload(ch);
/* done with HW */
return ATA_OP_FINISHED;
}
}
