static void cmd640_set_piomode(struct ata_port *ap, struct ata_device *adev) { struct cmd640_reg *timing = ap->private_data; struct pci_dev *pdev = to_pci_dev(ap->host->dev); struct ata_timing t; const unsigned long T = 1000000 / 33; const u8 setup_data[] = { 0x40, 0x40, 0x40, 0x80, 0x00 }; u8 reg; int arttim = ARTIM0 + 2 * adev->devno; struct ata_device *pair = ata_dev_pair(adev); if (ata_timing_compute(adev, adev->pio_mode, &t, T, 0) < 0) { printk(KERN_ERR DRV_NAME ": mode computation failed.\n"); return; } if (ap->port_no && pair) { struct ata_timing p; ata_timing_compute(pair, pair->pio_mode, &p, T, 1); ata_timing_merge(&p, &t, &t, ATA_TIMING_SETUP); } if (t.recover > 16) { t.active += t.recover - 16; t.recover = 16; } if (t.active > 16) t.active = 16; if (t.recover > 1) t.recover--; else t.recover = 15; if (t.setup > 4) t.setup = 0xC0; else t.setup = setup_data[t.setup]; if (ap->port_no == 0) { t.active &= 0x0F; pci_read_config_byte(pdev, arttim, ®); reg &= 0x3F; reg |= t.setup; pci_write_config_byte(pdev, arttim, reg); pci_write_config_byte(pdev, arttim + 1, (t.active << 4) | t.recover); } else { pci_read_config_byte(pdev, ARTIM23, ®); reg &= 0x3F; reg |= t.setup; pci_write_config_byte(pdev, ARTIM23, reg); timing->reg58[adev->devno] = (t.active << 4) | t.recover; } }
static void atp867x_set_piomode(struct ata_port *ap, struct ata_device *adev) { struct ata_device *peer = ata_dev_pair(adev); struct atp867x_priv *dp = ap->private_data; u8 speed = adev->pio_mode; struct ata_timing t, p; int T, UT; u8 b; T = 1000000000 / 33333; UT = T / 4; ata_timing_compute(adev, speed, &t, T, UT); if (peer && peer->pio_mode) { ata_timing_compute(peer, peer->pio_mode, &p, T, UT); ata_timing_merge(&p, &t, &t, ATA_TIMING_8BIT); } b = ioread8(dp->dma_mode); if (adev->devno & 1) b = (b & ~ATP867X_IO_DMAMODE_SLAVE_MASK); else b = (b & ~ATP867X_IO_DMAMODE_MSTR_MASK); iowrite8(b, dp->dma_mode); b = atp867x_get_active_clocks_shifted(ap, t.active) | atp867x_get_recover_clocks_shifted(t.recover); if (adev->devno & 1) iowrite8(b, dp->slave_piospd); else iowrite8(b, dp->mstr_piospd); b = atp867x_get_active_clocks_shifted(ap, t.act8b) | atp867x_get_recover_clocks_shifted(t.rec8b); iowrite8(b, dp->eightb_piospd); }
static void cmd64x_set_timing(struct ata_port *ap, struct ata_device *adev, u8 mode) { struct pci_dev *pdev = to_pci_dev(ap->host->dev); struct ata_timing t; const unsigned long T = 1000000 / 33; const u8 setup_data[] = { 0x40, 0x40, 0x40, 0x80, 0x00 }; u8 reg; /* Port layout is not logical so use a table */ const u8 arttim_port[2][2] = { { ARTTIM0, ARTTIM1 }, { ARTTIM23, ARTTIM23 } }; const u8 drwtim_port[2][2] = { { DRWTIM0, DRWTIM1 }, { DRWTIM2, DRWTIM3 } }; int arttim = arttim_port[ap->port_no][adev->devno]; int drwtim = drwtim_port[ap->port_no][adev->devno]; /* ata_timing_compute is smart and will produce timings for MWDMA that don't violate the drives PIO capabilities. */ if (ata_timing_compute(adev, mode, &t, T, 0) < 0) { printk(KERN_ERR DRV_NAME ": mode computation failed.\n"); return; } if (ap->port_no) { /* Slave has shared address setup */ struct ata_device *pair = ata_dev_pair(adev); if (pair) { struct ata_timing tp; ata_timing_compute(pair, pair->pio_mode, &tp, T, 0); ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); } } printk(KERN_DEBUG DRV_NAME ": active %d recovery %d setup %d.\n", t.active, t.recover, t.setup); if (t.recover > 16) { t.active += t.recover - 16; t.recover = 16; } if (t.active > 16) t.active = 16; /* Now convert the clocks into values we can actually stuff into the chip */ if (t.recover == 16) t.recover = 0; else if (t.recover > 1) t.recover--; else t.recover = 15; if (t.setup > 4) t.setup = 0xC0; else t.setup = setup_data[t.setup]; t.active &= 0x0F; /* 0 = 16 */ /* Load setup timing */ pci_read_config_byte(pdev, arttim, ®); reg &= 0x3F; reg |= t.setup; pci_write_config_byte(pdev, arttim, reg); /* Load active/recovery */ pci_write_config_byte(pdev, drwtim, (t.active << 4) | t.recover); }
static void cmd640_set_piomode(struct ata_port *ap, struct ata_device *adev) { struct cmd640_reg *timing = ap->private_data; struct pci_dev *pdev = to_pci_dev(ap->host->dev); struct ata_timing t; const unsigned long T = 1000000 / 33; const u8 setup_data[] = { 0x40, 0x40, 0x40, 0x80, 0x00 }; u8 reg; int arttim = ARTIM0 + 2 * adev->devno; struct ata_device *pair = ata_dev_pair(adev); if (ata_timing_compute(adev, adev->pio_mode, &t, T, 0) < 0) { printk(KERN_ERR DRV_NAME ": mode computation failed.\n"); return; } /* The second channel has shared timings and the setup timing is messy to switch to merge it for worst case */ if (ap->port_no && pair) { struct ata_timing p; ata_timing_compute(pair, pair->pio_mode, &p, T, 1); ata_timing_merge(&p, &t, &t, ATA_TIMING_SETUP); } /* Make the timings fit */ if (t.recover > 16) { t.active += t.recover - 16; t.recover = 16; } if (t.active > 16) t.active = 16; /* Now convert the clocks into values we can actually stuff into the chip */ if (t.recover > 1) t.recover--; /* 640B only */ else t.recover = 15; if (t.setup > 4) t.setup = 0xC0; else t.setup = setup_data[t.setup]; if (ap->port_no == 0) { t.active &= 0x0F; /* 0 = 16 */ /* Load setup timing */ pci_read_config_byte(pdev, arttim, ®); reg &= 0x3F; reg |= t.setup; pci_write_config_byte(pdev, arttim, reg); /* Load active/recovery */ pci_write_config_byte(pdev, arttim + 1, (t.active << 4) | t.recover); } else { /* Save the shared timings for channel, they will be loaded by qc_issue. Reloading the setup time is expensive so we keep a merged one loaded */ pci_read_config_byte(pdev, ARTIM23, ®); reg &= 0x3F; reg |= t.setup; pci_write_config_byte(pdev, ARTIM23, reg); timing->reg58[adev->devno] = (t.active << 4) | t.recover; } }