/* Set the timeout value in the watchdog register */
void ath_set_wd_timer(uint32_t usec /* micro seconds */)
{
#if defined(CONFIG_MACH_QCA956x)
uint32_t vTmpusec = 0;
uint32_t vCnt = 0;
#endif
#if defined(CONFIG_MACH_AR934x) || defined(CONFIG_MACH_QCA955x) || \
defined(CONFIG_MACH_QCA953x) || defined(CONFIG_MACH_QCA956x)
usec = usec * (ath_ref_freq / USEC_PER_SEC);
#else
usec = usec * (ath_ahb_freq / USEC_PER_SEC);
#endif
wddbg("%s: 0x%08x\n", __func__, usec);
#if defined(CONFIG_MACH_QCA956x)
//EV[131847], wait WDT timer write in( wait limit time )
vTmpusec = ath_reg_rd(ATH_WATCHDOG_TMR);
ath_reg_wr(ATH_WATCHDOG_TMR, usec);
while(ath_reg_rd(ATH_WATCHDOG_TMR) <= vTmpusec)
{
vCnt++;
if(vCnt >= 100)
{
printk("%s: Write WDT Timer fail !\n",__func__);
break;
}
}
#else
ath_reg_wr(ATH_WATCHDOG_TMR, usec);
#endif
}
void ath_config_slave_mdio_gpios(void)
{
unsigned int mask;
/* Slave MDIO phy address setting */
ath_reg_wr(MDIO_PHY_ADDR_ADDRESS, ATH_MDIO_PHY_ADDR);
/* Set the Clock Divisor */
mask = ath_reg_rd(ATH_MDIO_MAC_MII_MGMT_CFG) & ~(0xf);
mask |= ATH_MDIO_MGMT_CFG_CLK_DIV_28;
ath_reg_wr(ATH_MDIO_MAC_MII_MGMT_CFG, mask);
#ifndef CONFIG_MACH_QCA956x
/* Set External MDIO Multiplexing Register */
mask = ath_reg_rd(ATH_GPIO_IN_ENABLE3) &
~(GPIO_IN_ENABLE3_BOOT_EXT_MDC_MASK |
GPIO_IN_ENABLE3_BOOT_EXT_MDO_MASK);
mask |= GPIO_IN_ENABLE3_BOOT_EXT_MDC_SET(ATH_MDC_GPIO_PIN) |
GPIO_IN_ENABLE3_BOOT_EXT_MDO_SET(ATH_MDIO_GPIO_PIN);
ath_reg_wr(ATH_GPIO_IN_ENABLE3, mask);
#endif
/* Configure the Direction of GPIO Pins */
ath_gpio_config_input(ATH_MDC_GPIO_PIN);
ath_gpio_config_output(ATH_MDIO_GPIO_PIN);
/* Configure GPIO Output function as GPIOs */
ath_gpio_set_fn(ATH_MDIO_GPIO_PIN, ATH_MDIO_OUPUT_FUNC);
}
void ap_usb_led_on(void)
{
#ifdef CONFIG_MACH_AR934x
#if !defined(CONFIG_I2S) && defined(AP_USB_LED_GPIO)
unsigned int rddata;
if(AP_USB_LED_GPIO == 4) {
rddata = ath_reg_rd(ATH_GPIO_OUT_FUNCTION1); //87- for USB suspend
rddata = rddata & 0xffffff00;
rddata = rddata | ATH_GPIO_OUT_FUNCTION1_ENABLE_GPIO_4(0x0);
ath_reg_wr(ATH_GPIO_OUT_FUNCTION1, rddata);
}else if(AP_USB_LED_GPIO == 11) {
rddata = ath_reg_rd(ATH_GPIO_OUT_FUNCTION2); //87- for USB suspend
rddata = rddata & 0x00ffffff;
rddata = rddata | ATH_GPIO_OUT_FUNCTION2_ENABLE_GPIO_11(0x0);
ath_reg_wr(ATH_GPIO_OUT_FUNCTION2, rddata);
}
ath_reg_rmw_clear(ATH_GPIO_OE, (1<<AP_USB_LED_GPIO));
ath_reg_rmw_clear(ATH_GPIO_OUT, (1<<AP_USB_LED_GPIO));
#endif
#else
ath_gpio_out_val(AP_USB_LED_GPIO, USB_LED_ON);
#endif
}
void ath_gpio_config_int(int gpio,
ath_gpio_int_type_t type,
ath_gpio_int_pol_t polarity)
{
u32 val;
/*
* allow edge sensitive/rising edge too
*/
if (type == INT_TYPE_LEVEL) {
/* level sensitive */
ath_reg_rmw_set(ATH_GPIO_INT_TYPE, (1 << gpio));
} else {
/* edge triggered */
val = ath_reg_rd(ATH_GPIO_INT_TYPE);
val &= ~(1 << gpio);
ath_reg_wr(ATH_GPIO_INT_TYPE, val);
}
if (polarity == INT_POL_ACTIVE_HIGH) {
ath_reg_rmw_set(ATH_GPIO_INT_POLARITY, (1 << gpio));
} else {
val = ath_reg_rd(ATH_GPIO_INT_POLARITY);
val &= ~(1 << gpio);
ath_reg_wr(ATH_GPIO_INT_POLARITY, val);
}
ath_reg_rmw_set(ATH_GPIO_INT_ENABLE, (1 << gpio));
}
void ath_gpio_config(void)
{
#if 0
/* Disable clock obs */
ath_reg_wr (AR7240_GPIO_FUNC, (ath_reg_rd(AR7240_GPIO_FUNC) & 0xffe7e0ff));
/* Enable eth Switch LEDs */
#ifdef CONFIG_K31
ath_reg_wr (AR7240_GPIO_FUNC, (ath_reg_rd(AR7240_GPIO_FUNC) | 0xd8));
#else
ath_reg_wr (AR7240_GPIO_FUNC, (ath_reg_rd(AR7240_GPIO_FUNC) | 0xfa));
#endif
#endif
}
int __init athwdt_init(void)
{
int ret;
uint32_t *sram = KSEG1ADDR(ATH_SRAM_BASE + 0x934);
extern void ath_gpio_config_input(int);
#ifdef CONFIG_MACH_AR934x
extern void athwdt_timer_init(void);
#endif
printk("%s: Registering WDT ", __func__);
if ((ret = misc_register(&athwdt_miscdev))) {
printk("failed %d\n", ret);
return ret;
} else {
printk("success\n");
}
if (ath_reg_rd(RST_WATCHDOG_TIMER_CONTROL_ADDRESS) &
RST_WATCHDOG_TIMER_CONTROL_LAST_MASK) {
*sram = (*sram + 1);
printk("Watchdog Reset count: %u\n", *sram);
} else {
*sram = 0;
}
#ifdef CONFIG_MACH_AR934x
athwdt_timer_init();
#endif
ath_gpio_config_input(ATH_GPIO_RESET);
return 0;
}
int
ath_mem_config(void)
{
unsigned int type, reg32, *tap;
extern uint32_t *ath_ddr_tap_cal(void);
#if !defined(CONFIG_ATH_EMULATION)
type = ath_ddr_initial_config(CFG_DDR_REFRESH_VAL);
tap = ath_ddr_tap_cal();
prmsg("tap = 0x%p\n", tap);
tap = (uint32_t *)0xbd007f10;
prmsg("Tap (low, high) = (0x%x, 0x%x)\n", tap[0], tap[1]);
tap = (uint32_t *)TAP_CONTROL_0_ADDRESS;
prmsg("Tap values = (0x%x, 0x%x, 0x%x, 0x%x)\n",
tap[0], tap[2], tap[2], tap[3]);
/* Take WMAC out of reset */
reg32 = ath_reg_rd(RST_RESET_ADDRESS);
reg32 = reg32 & ~RST_RESET_RTC_RESET_SET(1);
ath_reg_wr_nf(RST_RESET_ADDRESS, reg32);
ath_usb1_initial_config();
ath_usb2_initial_config();
ath_gpio_config();
#endif /* !defined(CONFIG_ATH_EMULATION) */
return ath_ddr_find_size();
}
void
ath_usb1_initial_config(void)
{
#define unset(a) (~(a))
ath_reg_wr_nf(SWITCH_CLOCK_SPARE_ADDRESS,
ath_reg_rd(SWITCH_CLOCK_SPARE_ADDRESS) |
SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_SET(5));
udelay(1000);
ath_reg_rmw_set(RST_RESET_ADDRESS,
RST_RESET_USB_PHY_SUSPEND_OVERRIDE_SET(1));
udelay(1000);
ath_reg_rmw_clear(RST_RESET_ADDRESS, RST_RESET_USB_PHY_RESET_SET(1));
udelay(1000);
ath_reg_rmw_clear(RST_RESET_ADDRESS, RST_RESET_USB_PHY_ARESET_SET(1));
udelay(1000);
ath_reg_rmw_clear(RST_RESET_ADDRESS, RST_RESET_USB_HOST_RESET_SET(1));
udelay(1000);
ath_reg_rmw_clear(RST_RESET_ADDRESS, RST_RESET_USB_PHY_PLL_PWD_EXT_SET(1));
udelay(10);
ath_reg_rmw_set(RST_RESET2_ADDRESS, RST_RESET2_USB1_EXT_PWR_SEQ_SET(1));
udelay(10);
}
static int
ath_pci_read_config(struct pci_controller *hose,
pci_dev_t dev, int where, uint32_t *value)
{
*value = ath_reg_rd(ATH_PCI_DEV_CFGBASE + where);
return 0;
}
unsigned
ath_hwcs_get(void)
{
unsigned status;
if (!ath_start_csum)
return 0x0bad0000u;
// Wait for masked intr
while (!((status = ath_reg_rd(ATH_HWCS_DMATX_DESC_STATUS)) & ATH_HWCS_TX_DESC_INTR));
// ack the intr
ath_reg_wr(ATH_HWCS_DMATX_DESC_STATUS, status & ATH_HWCS_TX_DESC_INTR);
ath_start_csum = 0;
#ifdef CONFIG_ATH_HWCS_debug
if (((uncached_cksum_desc->info.control.pktSize) & 0xffff) !=
((ath_hwcs_tx_desc->info.control.pktSize) & 0xffff)) {
printk("cache prob uncached read 0x%x cached read 0x%x\n",
((uncached_cksum_desc->info.control.pktSize) & 0xffff),
((ath_hwcs_tx_desc->info.control.pktSize) & 0xffff));
}
#endif
return ath_hwcs_get_csum_from_desc(ath_hwcs_tx_desc);
}
void __init plat_mem_setup(void)
{
#if 1
board_be_handler = ath_be_handler;
#endif
_machine_restart = ath_restart;
_machine_halt = ath_halt;
pm_power_off = ath_power_off;
/*
** early_serial_setup seems to conflict with serial8250_register_port()
** In order for console to work, we need to call register_console().
** We can call serial8250_register_port() directly or use
** platform_add_devices() function which eventually calls the
** register_console(). AP71 takes this approach too. Only drawback
** is if system screws up before we register console, we won't see
** any msgs on the console. System being stable now this should be
** a special case anyways. Just initialize Uart here.
*/
#ifdef CONFIG_SERIAL_8250
UartInit();
#endif
#ifdef CONFIG_MACH_AR933x
/* clear wmac reset */
ath_reg_wr(ATH_RESET,
(ath_reg_rd(ATH_RESET) & (~ATH_RESET_WMAC)));
#endif
serial_print("Booting %s\n", get_system_type());
}
static int
ath_pci_read_config_rc2(struct pci_controller *hose,
pci_dev_t dev, int where, uint32_t *value)
{
*value = ath_reg_rd(0xb6000000 + where);
return 0;
}
/* Return the value present in the watchdog register */
static inline uint32_t ath_get_wd_timer(void)
{
uint32_t val;
val = (uint32_t) ath_reg_rd(ATH_WATCHDOG_TMR);
val = (val * USEC_PER_SEC) / ath_ahb_freq;
return val;
}
void ath_restart(char *command)
{
for (;;) {
if (is_ar934x_10()) {
ath_reg_wr(ATH_GPIO_OE, ath_reg_rd(ATH_GPIO_OE) & (~(1 << 17)));
} else {
ath_reg_wr(ATH_RESET, RST_RESET_FULL_CHIP_RESET_MASK);
}
}
}
int __init ath_simple_config_init(void)
{
#if 0
#ifdef CONFIG_CUS100
u32 mask = 0;
#endif
int req, ret;
ret = misc_register(&athfr_miscdev);
if (ret < 0) {
printk("*** ath misc_register failed %d *** \n", ret);
return -1;
}
#ifdef CONFIG_CUS100
mask = ath_reg_rd(ATH_MISC_INT_MASK);
ath_reg_wr(ATH_MISC_INT_MASK, mask | (1 << 2));
ath_gpio_config_int(JUMPSTART_GPIO, INT_TYPE_LEVEL,
INT_POL_ACTIVE_HIGH);
ath_gpio_intr_enable(JUMPSTART_GPIO);
ath_gpio_config_input(JUMPSTART_GPIO);
#else
ath_gpio_config_input(JUMPSTART_GPIO);
/* configure Jumpstart GPIO as level triggered interrupt */
ath_gpio_config_int(JUMPSTART_GPIO, INT_TYPE_LEVEL,
INT_POL_ACTIVE_LOW);
printk("%s JUMPSTART_GPIO: %d\n", __func__, JUMPSTART_GPIO);
#ifndef CONFIG_MACH_AR934x
ath_reg_rmw_clear(ATH_GPIO_FUNCTIONS, (1 << 2));
ath_reg_rmw_clear(ATH_GPIO_FUNCTIONS, (1 << 16));
ath_reg_rmw_clear(ATH_GPIO_FUNCTIONS, (1 << 20));
#endif
#endif
req = request_irq(ATH_GPIO_IRQn(JUMPSTART_GPIO), jumpstart_irq, 0,
"SW JUMPSTART/FACTORY RESET", NULL);
if (req != 0) {
printk("request_irq for jumpstart failed (error %d)\n", req);
misc_deregister(&athfr_miscdev);
ath_gpio_intr_shutdown(ATH_GPIO_IRQn(JUMPSTART_GPIO));
return -1;
}
#if !defined(CONFIG_I2S) && defined(AP_USB_LED_GPIO)
ath_gpio_config_output(AP_USB_LED_GPIO);
#endif
init_waitqueue_head(&ath_fr_wq);
#endif
create_simple_config_led_proc_entry();
return 0;
}
void ath_dispatch_wlan_intr(void)
{
u_int32_t int_status = ath_reg_rd(ATH_WMAC_INT_STATUS);
#ifdef CONFIG_PCI
if (int_status & ATH_PCIE_INT_MASK) {
do_IRQ(ATH_PCI_IRQ_DEV0);
}
#endif
if (int_status & ATH_AHB_WMAC_INT_MASK) {
do_IRQ(ATH_CPU_IRQ_WLAN);
}
}
void
ath_sys_frequency(void)
{
#if !defined(CONFIG_ATH_EMULATION)
uint32_t pll, out_div, ref_div, nint, frac, clk_ctrl;
#endif
uint32_t ref;
if (ath_cpu_freq)
return;
if ((ath_reg_rd(ATH_BOOTSTRAP_REG) & ATH_REF_CLK_40)) {
ref = (40 * 1000000);
} else {
ref = (25 * 1000000);
}
ath_uart_freq = ath_ref_freq = ref;
#ifdef CONFIG_ATH_EMULATION
ath_cpu_freq = 80000000;
ath_ddr_freq = 80000000;
ath_ahb_freq = 40000000;
#else
printk("%s: ", __func__);
clk_ctrl = ath_reg_rd(ATH_DDR_CLK_CTRL);
pll = ath_reg_rd(CPU_DPLL2_ADDRESS);
if (CPU_DPLL2_LOCAL_PLL_GET(pll)) {
out_div = CPU_DPLL2_OUTDIV_GET(pll);
pll = ath_reg_rd(CPU_DPLL_ADDRESS);
nint = CPU_DPLL_NINT_GET(pll);
frac = CPU_DPLL_NFRAC_GET(pll);
ref_div = CPU_DPLL_REFDIV_GET(pll);
pll = ref >> 18;
frac = frac * pll / ref_div;
printk("cpu srif ");
} else {
void
pci_rc2_init_board (void)
{
uint32_t cmd;
ath_reg_rmw_set(RST_RESET2_ADDRESS, RST_RESET2_PCIE2_PHY_RESET_SET(1));
udelay(10000);
ath_reg_rmw_set(RST_RESET2_ADDRESS, RST_RESET2_PCIE2_RESET_SET(1));
udelay(10000);
ath_reg_rmw_clear(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY2_SET(1));
udelay(10000);
ath_reg_wr_nf(PCIE2_RESET_ADDRESS, 0); // Put endpoint in reset
udelay(100000);
ath_reg_rmw_set(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY2_SET(1));
udelay(10000);
ath_reg_rmw_clear(RST_RESET2_ADDRESS, RST_RESET_PCIE_PHY_RESET_SET(1));
udelay(10000);
ath_reg_rmw_clear(RST_RESET2_ADDRESS, RST_RESET_PCIE_RESET_SET(1));
udelay(10000);
ath_reg_wr_nf(PCIE2_APP_ADDRESS, PCIE2_APP_PCIE2_BAR_MSN_SET(1) |
PCIE2_APP_CFG_BE_SET(0xf) |
PCIE2_APP_SLV_RESP_ERR_MAP_SET(0x3f) |
PCIE2_APP_LTSSM_ENABLE_SET(1));
cmd = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE |
PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
ath_local_write_config_rc2(PCI_COMMAND, 4, cmd);
ath_local_write_config_rc2(0x20, 4, 0x1ff01000);
ath_local_write_config_rc2(0x24, 4, 0x1ff01000);
ath_reg_wr_nf(PCIE2_RESET_ADDRESS, 4); // Pull endpoint out of reset
udelay(100000);
/*
* Check if the WLAN PCI-E H/W is present, If the
* WLAN H/W is not present, skip the PCI platform
* initialization code and return
*/
if (((ath_reg_rd(PCIE2_RESET_ADDRESS)) & 0x1) == 0x0) {
printf("*** Warning *** : PCIe WLAN Module not found !!!\n");
return;
}
}
void
ath_gpio_set_fn(int gpio, int fn)
{
#define gpio_fn_reg(x) ((x) / 4)
#define gpio_lsb(x) (((x) % 4) * 8)
#define gpio_msb(x) (gpio_lsb(x) + 7)
#define gpio_mask(x) (0xffu << gpio_lsb(x))
#define gpio_set(x, f) (((f) & 0xffu) << gpio_lsb(x))
uint32_t *reg = ((uint32_t *)GPIO_OUT_FUNCTION0_ADDRESS) +
gpio_fn_reg(gpio);
ath_reg_wr(reg, (ath_reg_rd(reg) & ~gpio_mask(gpio)) | gpio_set(gpio, fn));
}
void ath_spi_raw_output_u8(unsigned char val)
{
int ii;
unsigned int cs;
cs = ath_reg_rd(ATH_SPI_WRITE) & ~(ATH_SPI_D0_HIGH |
ATH_SPI_CLK_HIGH);
for (ii = 7; ii >= 0; ii--) {
unsigned char jj = (val >> ii) & 1;
ath_reg_wr_nf(ATH_SPI_WRITE, cs | jj);
ath_reg_wr_nf(ATH_SPI_WRITE,
cs | jj | ATH_SPI_CLK_HIGH);
}
}
static void ath_config_eth_led(void)
{
uint32_t reg_value;
/*WAN, GPIO19, DS3*/
ath_gpio_config_output(19);
ath_reg_rmw_clear(ATH_GPIO_OUT_FUNCTION4, 0xff<<24);
reg_value = ath_reg_rd(ATH_GPIO_OUT_FUNCTION4);
reg_value = reg_value | (41 << 24);
ath_reg_wr(ATH_GPIO_OUT_FUNCTION4, reg_value);
printk("ATH_GPIO_OUT_FUNCTION4: 0x%x\n", ath_reg_rd(ATH_GPIO_OUT_FUNCTION4));
/* LAN1, GPIO20, DS4 */
ath_gpio_config_output(20);
ath_reg_rmw_clear(ATH_GPIO_OUT_FUNCTION5, 0xff<<0);
reg_value = ath_reg_rd(ATH_GPIO_OUT_FUNCTION5);
reg_value = reg_value | (42 << 0);
ath_reg_wr(ATH_GPIO_OUT_FUNCTION5, reg_value);
/* it's ok */
/* LAN2, GPIO21, DS5 */
ath_gpio_config_output(21);
ath_reg_rmw_clear(ATH_GPIO_OUT_FUNCTION5, 0xff<<8);
reg_value = ath_reg_rd(ATH_GPIO_OUT_FUNCTION5);
reg_value = reg_value | (43 << 8);
ath_reg_wr(ATH_GPIO_OUT_FUNCTION5, reg_value);
printk("ATH_GPIO_OUT_FUNCTION5: 0x%x\n", ath_reg_rd(ATH_GPIO_OUT_FUNCTION5));
/* LAN3, GPIO12, DS6 */
ath_gpio_config_output(12);
ath_reg_rmw_clear(ATH_GPIO_OUT_FUNCTION3, 0xff<<0);
reg_value = ath_reg_rd(ATH_GPIO_OUT_FUNCTION3);
reg_value = reg_value | (44 << 0);
ath_reg_wr(ATH_GPIO_OUT_FUNCTION3, reg_value);
/* it's ok */
/* LAN4, GPIO18, DS7 */
ath_gpio_config_output(18);
ath_reg_rmw_clear(ATH_GPIO_OUT_FUNCTION4, 0xff<<16);
reg_value = ath_reg_rd(ATH_GPIO_OUT_FUNCTION4);
reg_value = reg_value | (45 << 16);
ath_reg_wr(ATH_GPIO_OUT_FUNCTION4, reg_value);
printk("ATH_GPIO_OUT_FUNCTION4: 0x%x\n", ath_reg_rd(ATH_GPIO_OUT_FUNCTION4));
}
void serial_init(void)
{
int revid = (ath_reg_rd(ATH_REV_ID) & ATH_REV_ID_MASK) >> 4;
switch(revid) {
case REV_ID_HORNET:
serial_putc = hornet_serial_putc;
break;
case REV_ID_WASP:
serial_putc = _ath_serial_putc;
break;
case REV_ID_SCO:
serial_putc = _ath_serial_putc;
break;
default:
/* die */
serial_putc = (void *) 0xbadca11;
break;
}
}
unsigned int ath_spi_raw_input_u8(void)
{
unsigned int i, j;
for (i = 0; i < 8; i++) // TRANSMIT DATA
{
ath_reg_wr(0xbf000008, 0x50100); //CS1 = 0 , CLK=1
for (j = 0; j < 15; j++) {;
};
ath_reg_wr(0xbf000008, 0x50000); //CS1 = 0 , CLK=0
for (j = 0; j < 15; j++) {;
};
}
ath_reg_wr(0xbf000008, 0x70000); //CS1 = 1 , CLK=0
for (j = 0; j < 15; j++) {;
};
return ath_reg_rd(ATH_SPI_RD_STATUS) & 0xff;
}
static int
ath_local_read_config_rc2(int where, int size, uint32_t *value)
{
*value = ath_reg_rd(0x18250000 + where);
return 0;
}
void
pci_rc2_init_board (void)
{
#if defined(CONFIG_MACH_QCA956x)
ath_reg_rmw_clear(GPIO_OE_ADDRESS, 0x1);
udelay(10000);
ath_reg_rmw_set(GPIO_OUT_FUNCTION0_ADDRESS, GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_SET(0x73));
udelay(10000);
ath_reg_rmw_set(RST_RESET_ADDRESS,RST_RESET_PCIE_PHY_RESET_SET(1) |
RST_RESET_PCIE_RESET_SET(1));
udelay(10000);
ath_reg_rmw_clear(RST_RESET_ADDRESS,RST_RESET_PCIE_PHY_RESET_SET(1) |
RST_RESET_PCIE_RESET_SET(1));
udelay(10000);
ath_reg_rmw_set(RST_RESET2_ADDRESS,RST_RESET_PCIE_PHY_RESET_SET(1) |
RST_RESET_PCIE_RESET_SET(1));
udelay(10000);
ath_reg_rmw_clear(RST_RESET2_ADDRESS,RST_RESET_PCIE_PHY_RESET_SET(1) |
RST_RESET_PCIE_RESET_SET(1));
udelay(10000);
ath_reg_wr(PCIE2_RESET_ADDRESS,PCIE2_RESET_EP_RESET_L_SET(1));
udelay(10000);
ath_reg_wr(ATH_PCI_CRP_WRDATA,0x6);
udelay(10000);
ath_reg_wr(PCIE_APP_ADDRESS,PCIE_APP_LTSSM_ENABLE_SET(1) |
PCIE_APP_SLV_RESP_ERR_MAP_SET(0x3f) |
PCIE_APP_CFG_BE_SET(0xf) |
PCIE_APP_PCIE_BAR_MSN_SET(1));
udelay(10000);
ath_reg_wr(PCIE_INT_MASK_ADDRESS,PCIE_INT_MASK_CORR_ERR_SET(1) |
PCIE_INT_MASK_NONFATAL_ERR_SET(1) |
PCIE_INT_MASK_FATAL_ERR_SET(1) |
PCIE_INT_MASK_GM_COMP_LOOKUP_ERR_SET(1) |
PCIE_INT_MASK_RADMX_COMP_LOOKUP_ERR_SET(1) |
PCIE_INT_MASK_INTA_SET(1) |
PCIE_INT_MASK_INTB_SET(1) |
PCIE_INT_MASK_INTC_SET(1) |
PCIE_INT_MASK_INTD_SET(1) |
PCIE_INT_MASK_MSI_SET(1) |
PCIE_INT_MASK_MSI_ERR_SET(1) |
PCIE_INT_MASK_AER_INT_SET(1) |
PCIE_INT_MASK_AER_MSI_SET(1) |
PCIE_INT_MASK_SYS_ERR_SET(1) |
PCIE_INT_MASK_INTAL_SET(1) |
PCIE_INT_MASK_INTBL_SET(1) |
PCIE_INT_MASK_INTCL_SET(1) |
PCIE_INT_MASK_INTDL_SET(1));
udelay(10000);
ath_local_write_config_rc2(0x70c, 4, 0x1b403200);
udelay(10000);
ath_reg_wr(PCIE_DEBUG_ADDRESS,PCIE_DEBUG_BYTESWAP_SET(1));
udelay(10000);
ath_reg_rmw_set(XTAL2_SEC_ADDRESS, XTAL2_SEC_SPARE_SET(0xc));
udelay(10000);
ath_reg_rmw_clear(PCIe_DPLL2_ADDRESS, PCIe_DPLL2_KI_SET(0x3) |
PCIe_DPLL2_KD_SET(0xF));
udelay(10000);
ath_reg_rmw_set(PCIe_DPLL2_ADDRESS, PCIe_DPLL2_KD_SET(0x4));
udelay(10000);
#else
uint32_t cmd;
ath_reg_rmw_set(RST_RESET2_ADDRESS, RST_RESET2_PCIE2_PHY_RESET_SET(1));
udelay(10000);
ath_reg_rmw_set(RST_RESET2_ADDRESS, RST_RESET2_PCIE2_RESET_SET(1));
udelay(10000);
ath_reg_rmw_clear(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY2_SET(1));
udelay(10000);
ath_reg_wr_nf(PCIE2_RESET_ADDRESS, 0); // Put endpoint in reset
udelay(100000);
ath_reg_rmw_set(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY2_SET(1));
udelay(10000);
ath_reg_rmw_clear(RST_RESET2_ADDRESS, RST_RESET_PCIE_PHY_RESET_SET(1));
udelay(10000);
ath_reg_rmw_clear(RST_RESET2_ADDRESS, RST_RESET_PCIE_RESET_SET(1));
udelay(10000);
ath_reg_wr_nf(PCIE2_APP_ADDRESS, PCIE2_APP_PCIE2_BAR_MSN_SET(1) |
PCIE2_APP_CFG_BE_SET(0xf) |
PCIE2_APP_SLV_RESP_ERR_MAP_SET(0x3f) |
PCIE2_APP_LTSSM_ENABLE_SET(1));
cmd = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE |
PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
ath_local_write_config_rc2(PCI_COMMAND, 4, cmd);
ath_local_write_config_rc2(0x20, 4, 0x1ff01000);
ath_local_write_config_rc2(0x24, 4, 0x1ff01000);
ath_reg_wr_nf(PCIE2_RESET_ADDRESS, 4); // Pull endpoint out of reset
udelay(100000);
#endif
/*
* Check if the WLAN PCI-E H/W is present, If the
* WLAN H/W is not present, skip the PCI platform
* initialization code and return
*/
if (((ath_reg_rd(PCIE2_RESET_ADDRESS)) & 0x1) == 0x0) {
prmsg("*** Warning *** : PCIe WLAN Module not found !!!\n");
return;
}
}
static int
ath_local_read_config(int where, int size, uint32_t *value)
{
*value = ath_reg_rd(ATH_PCI_CRP + where);
return 0;
}
PCI_INIT_RET_TYPE
pci_init_board (void)
{
#ifdef CONFIG_ATH_EMULATION
prmsg("--- Skipping %s for emulation\n", __func__);
#else
uint32_t cmd;
if (is_drqfn() && !is_qca953x()) {
/*
* Dont enable PCIe in DRQFN package as it has some issues
* related to PCIe
*/
PCI_INIT_RETURN;
}
#if defined(CONFIG_MACH_QCA953x)
if (ath_reg_rd(RST_BOOTSTRAP_ADDRESS) & RST_BOOTSTRAP_TESTROM_ENABLE_MASK) {
ath_reg_rmw_clear(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY_SET(1));
ath_reg_wr(PCIE_PHY_REG_1_ADDRESS, PCIE_PHY_REG_1_RESET_1);
ath_reg_wr(PCIE_PHY_REG_3_ADDRESS, PCIE_PHY_REG_3_RESET_1);
ath_reg_rmw_set(PCIE_PWR_MGMT_ADDRESS, PCIE_PWR_MGMT_ASSERT_CLKREQN_SET(1));
ath_reg_rmw_set(PCIE_PLL_CONFIG_ADDRESS, PCIE_PLL_CONFIG_PLLPWD_SET(1));
ath_reg_rmw_set(RST_RESET_ADDRESS, RST_RESET_PCIE_RESET_SET(1));
ath_reg_rmw_set(RST_RESET_ADDRESS, RST_RESET_PCIE_PHY_RESET_SET(1));
ath_reg_rmw_clear(RST_CLKGAT_EN_ADDRESS, RST_CLKGAT_EN_PCIE_RC_SET(1));
PCI_INIT_RETURN;
} else {
/* Honeybee -The PCIe reference clock frequency is being changed
to vary from 99.968MHz to 99.999MHz using SS modulation */
ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MAX_ADDRESS,
PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_SET(0x1) |
PCIE_PLL_DITHER_DIV_MAX_USE_MAX_SET(0x1) |
PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_SET(0x17) |
PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_SET(0x3fff));
ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MIN_ADDRESS,
PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_SET(0x3f84)|
PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_SET(0x17));
}
#else
#if defined(CONFIG_MACH_QCA956x)
ath_reg_rmw_set(PCIE_PHY_REG_1_ADDRESS, PCIE_PHY_REG_1_S_SET(PCIE_PHY_REG_1_S_RESET));
ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MAX_ADDRESS,
PCIE_PLL_DITHER_DIV_MAX_USE_MAX_SET(0x1) |
PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_SET(0x17) |
PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_SET(0x3fff));
ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MIN_ADDRESS,
PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_SET(0x3f84) |
PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_SET(0x17));
#else
// common for rc1 and rc2
ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MAX_ADDRESS,
PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_SET(0x1) |
PCIE_PLL_DITHER_DIV_MAX_USE_MAX_SET(0x1) |
PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_SET(0x14) |
PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_SET(0x3ff));
ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MIN_ADDRESS,
PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_SET(0x14));
#endif
#endif
ath_reg_wr_nf(PCIE_PLL_CONFIG_ADDRESS,
PCIE_PLL_CONFIG_REFDIV_SET(1) |
PCIE_PLL_CONFIG_BYPASS_SET(1) |
PCIE_PLL_CONFIG_PLLPWD_SET(1));
udelay(10000);
ath_reg_rmw_clear(PCIE_PLL_CONFIG_ADDRESS, PCIE_PLL_CONFIG_PLLPWD_SET(1));
udelay(1000);
ath_reg_rmw_clear(PCIE_PLL_CONFIG_ADDRESS, PCIE_PLL_CONFIG_BYPASS_SET(1));
udelay(1000);
#if !defined(CONFIG_MACH_QCA956x)
#ifdef PCIE2_APP_ADDRESS
if (!(ath_reg_rd(RST_BOOTSTRAP_ADDRESS) & RST_BOOTSTRAP_PCIE_RC_EP_SELECT_MASK)) {
pci_rc2_init_board();
return;
}
#endif
ath_reg_rmw_set(RST_RESET_ADDRESS, RST_RESET_PCIE_PHY_RESET_SET(1));
udelay(10000);
ath_reg_rmw_set(RST_RESET_ADDRESS, RST_RESET_PCIE_RESET_SET(1));
udelay(10000);
#ifdef PCIE2_APP_ADDRESS
ath_reg_rmw_clear(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY_SET(1));
udelay(10000);
#endif
ath_reg_wr_nf(PCIE_RESET_ADDRESS, 0); // Put endpoint in reset
udelay(100000);
#ifdef PCIE2_APP_ADDRESS
ath_reg_rmw_set(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY_SET(1));
udelay(10000);
#endif
ath_reg_rmw_clear(RST_RESET_ADDRESS, RST_RESET_PCIE_PHY_RESET_SET(1));
udelay(10000);
ath_reg_rmw_clear(RST_RESET_ADDRESS, RST_RESET_PCIE_RESET_SET(1));
udelay(10000);
ath_reg_wr_nf(PCIE_APP_ADDRESS, PCIE_APP_PCIE_BAR_MSN_SET(1) |
PCIE_APP_CFG_BE_SET(0xf) |
PCIE_APP_SLV_RESP_ERR_MAP_SET(0x3f) |
PCIE_APP_LTSSM_ENABLE_SET(1));
cmd = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE |
PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
ath_local_write_config(PCI_COMMAND, 4, cmd);
ath_local_write_config(0x20, 4, 0x1ff01000);
ath_local_write_config(0x24, 4, 0x1ff01000);
ath_reg_wr_nf(PCIE_RESET_ADDRESS, 4); // Pull endpoint out of reset
udelay(100000);
/*
* Check if the WLAN PCI-E H/W is present, If the
* WLAN H/W is not present, skip the PCI platform
* initialization code and return
*/
if (((ath_reg_rd(PCIE_RESET_ADDRESS)) & 0x1) == 0x0) {
prmsg("*** Warning *** : PCIe WLAN Module not found !!!\n");
}
#endif
#ifdef PCIE2_APP_ADDRESS
pci_rc2_init_board();
#endif
#ifndef COMPRESSED_UBOOT
/*
* Now, configure for u-boot tools
*/
hose.first_busno = 0;
hose.last_busno = 0xff;
/* System space */
pci_set_region( &hose.regions[0],
0x80000000,
0x00000000,
32 * 1024 * 1024,
PCI_REGION_MEM | PCI_REGION_MEMORY);
/* PCI memory space */
pci_set_region( &hose.regions[1],
0x10000000,
0x10000000,
128 * 1024 * 1024,
PCI_REGION_MEM);
hose.region_count = 2;
pci_register_hose(&hose);
pci_set_ops( &hose,
pci_hose_read_config_byte_via_dword,
pci_hose_read_config_word_via_dword,
ath_pci_read_config,
pci_hose_write_config_byte_via_dword,
pci_hose_write_config_word_via_dword,
ath_pci_write_config);
#endif
plat_dev_init();
#endif /* CONFIG_ATH_EMULATION */
PCI_INIT_RETURN;
}
unsigned int ath_slic_cntrl_rd(void)
{
return ath_reg_rd(ATH_SLIC_CTRL);
}
static inline uint32_t ath_get_wd_timer_last(void)
{
return ((uint32_t) (ath_reg_rd(ATH_WATCHDOG_TMR_CONTROL) &
ATH_WD_LAST_MASK) >> ATH_WD_LAST_SHIFT);
}
