void ath_usb1_initial_config(void) { #define unset(a) (~(a)) ath_reg_wr_nf(SWITCH_CLOCK_SPARE_ADDRESS, ath_reg_rd(SWITCH_CLOCK_SPARE_ADDRESS) | SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_SET(5)); udelay(1000); ath_reg_rmw_set(RST_RESET_ADDRESS, RST_RESET_USB_PHY_SUSPEND_OVERRIDE_SET(1)); udelay(1000); ath_reg_rmw_clear(RST_RESET_ADDRESS, RST_RESET_USB_PHY_RESET_SET(1)); udelay(1000); ath_reg_rmw_clear(RST_RESET_ADDRESS, RST_RESET_USB_PHY_ARESET_SET(1)); udelay(1000); ath_reg_rmw_clear(RST_RESET_ADDRESS, RST_RESET_USB_HOST_RESET_SET(1)); udelay(1000); ath_reg_rmw_clear(RST_RESET_ADDRESS, RST_RESET_USB_PHY_PLL_PWD_EXT_SET(1)); udelay(10); ath_reg_rmw_set(RST_RESET2_ADDRESS, RST_RESET2_USB1_EXT_PWR_SEQ_SET(1)); udelay(10); }
void ath_gpio_config_int(int gpio, ath_gpio_int_type_t type, ath_gpio_int_pol_t polarity) { u32 val; /* * allow edge sensitive/rising edge too */ if (type == INT_TYPE_LEVEL) { /* level sensitive */ ath_reg_rmw_set(ATH_GPIO_INT_TYPE, (1 << gpio)); } else { /* edge triggered */ val = ath_reg_rd(ATH_GPIO_INT_TYPE); val &= ~(1 << gpio); ath_reg_wr(ATH_GPIO_INT_TYPE, val); } if (polarity == INT_POL_ACTIVE_HIGH) { ath_reg_rmw_set(ATH_GPIO_INT_POLARITY, (1 << gpio)); } else { val = ath_reg_rd(ATH_GPIO_INT_POLARITY); val &= ~(1 << gpio); ath_reg_wr(ATH_GPIO_INT_POLARITY, val); } ath_reg_rmw_set(ATH_GPIO_INT_ENABLE, (1 << gpio)); }
void pci_rc2_init_board (void) { uint32_t cmd; ath_reg_rmw_set(RST_RESET2_ADDRESS, RST_RESET2_PCIE2_PHY_RESET_SET(1)); udelay(10000); ath_reg_rmw_set(RST_RESET2_ADDRESS, RST_RESET2_PCIE2_RESET_SET(1)); udelay(10000); ath_reg_rmw_clear(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY2_SET(1)); udelay(10000); ath_reg_wr_nf(PCIE2_RESET_ADDRESS, 0); // Put endpoint in reset udelay(100000); ath_reg_rmw_set(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY2_SET(1)); udelay(10000); ath_reg_rmw_clear(RST_RESET2_ADDRESS, RST_RESET_PCIE_PHY_RESET_SET(1)); udelay(10000); ath_reg_rmw_clear(RST_RESET2_ADDRESS, RST_RESET_PCIE_RESET_SET(1)); udelay(10000); ath_reg_wr_nf(PCIE2_APP_ADDRESS, PCIE2_APP_PCIE2_BAR_MSN_SET(1) | PCIE2_APP_CFG_BE_SET(0xf) | PCIE2_APP_SLV_RESP_ERR_MAP_SET(0x3f) | PCIE2_APP_LTSSM_ENABLE_SET(1)); cmd = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK; ath_local_write_config_rc2(PCI_COMMAND, 4, cmd); ath_local_write_config_rc2(0x20, 4, 0x1ff01000); ath_local_write_config_rc2(0x24, 4, 0x1ff01000); ath_reg_wr_nf(PCIE2_RESET_ADDRESS, 4); // Pull endpoint out of reset udelay(100000); /* * Check if the WLAN PCI-E H/W is present, If the * WLAN H/W is not present, skip the PCI platform * initialization code and return */ if (((ath_reg_rd(PCIE2_RESET_ADDRESS)) & 0x1) == 0x0) { printf("*** Warning *** : PCIe WLAN Module not found !!!\n"); return; } }
static void ath_pci_irq_enable(unsigned int irq) { #ifdef CONFIG_PERICOM /* Copied from NetBSD */ if (irq == ATH_PCI_IRQ_DEV0) { ath_reg_rmw_set(ATH_PCI_INT_MASK, ATH_PCI_INT_B_L); } else { ath_reg_rmw_set(ATH_PCI_INT_MASK, ATH_PCI_INT_C_L); } #else ath_reg_rmw_set(ATH_PCI_INT_MASK, ATH_PCI_INT_A_L); #endif /* CONFIG_PERICOM */ }
void uart_gpio_init_qca953x(void) { uint32_t val; ath_reg_rmw_set(GPIO_OE_ADDRESS, (1<<9)); ath_reg_rmw_clear(GPIO_OE_ADDRESS, (1<<10)); ath_reg_rmw_set(GPIO_OUT_FUNCTION2_ADDRESS, GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_SET(0x16)); ath_reg_rmw_clear(GPIO_IN_ENABLE0_ADDRESS, GPIO_IN_ENABLE0_UART_SIN_SET(0xff)); ath_reg_rmw_set(GPIO_IN_ENABLE0_ADDRESS, GPIO_IN_ENABLE0_UART_SIN_SET(0x9)); }
int ath_hwcs_init(void) { dma_addr_t pa; #ifdef CONFIG_ATH_HWCS_notyet if (!dmapool) { dmapool = dma_pool_create("csum_hw_accel", NULL, sizeof(ath_hwcs_desc_t), (size_t)4, (size_t)ATH_HWCS_DMAPOOL_SIZE); if (!dmapool) return -1; } #endif ath_hwcs_tx_desc = kmalloc(sizeof(ath_hwcs_desc_t), GFP_DMA); // Setup checksum descriptor pa = dma_map_single(NULL, ath_hwcs_tx_desc, sizeof(ath_hwcs_desc_t), DMA_TO_DEVICE); ath_hwcs_tx_desc->next = (ath_hwcs_desc_t *)pa; uncached_cksum_desc = (ath_hwcs_desc_t *)KSEG1ADDR(virt_to_phys(ath_hwcs_tx_desc)); // Weight for channels ath_reg_wr(ATH_HWCS_DMATX_ARB_CFG, (63 << 8)); // Tx checksum interrupt mask ath_reg_rmw_set(ATH_HWCS_IMASK, ATH_HWCS_TX_INTR_MASK); // Initialize Tx descriptor address ath_reg_wr(ATH_HWCS_DMATX_DESC0, pa); printk("%s: Init done ...\n", __func__); return 0; }
void ath_gpio_config_input(int gpio) { #ifdef CONFIG_MACH_AR934x ath_reg_rmw_set(ATH_GPIO_OE, (1 << gpio)); #else ath_reg_rmw_clear(ATH_GPIO_OE, (1 << gpio)); #endif }
void ath_gpio_out_val(int gpio, int val) { if (val & 0x1) { ath_reg_rmw_set(ATH_GPIO_OUT, (1 << gpio)); } else { ath_reg_rmw_clear(ATH_GPIO_OUT, (1 << gpio)); } }
void ap_usb_led_off(void) { #ifdef CONFIG_MACH_AR934x #if !defined(CONFIG_I2S) && defined(AP_USB_LED_GPIO) ath_reg_rmw_set(ATH_GPIO_OUT, (1<<AP_USB_LED_GPIO)); #endif #else ath_gpio_out_val(AP_USB_LED_GPIO, USB_LED_OFF); #endif }
void ath_gpio_config_input(int gpio) { #if defined(CONFIG_MACH_AR934x) || \ defined(CONFIG_MACH_QCA955x) || \ defined(CONFIG_MACH_QCA953x) || \ defined(CONFIG_MACH_QCA956x) ath_reg_rmw_set(ATH_GPIO_OE, (1 << gpio)); #else ath_reg_rmw_clear(ATH_GPIO_OE, (1 << gpio)); #endif }
void ath_usb2_initial_config(void) { ath_reg_rmw_set(RST_RESET2_ADDRESS, RST_RESET2_USB2_MODE_SET(1)); udelay(10); ath_reg_rmw_set(RST_RESET2_ADDRESS, RST_RESET2_USB_PHY2_SUSPEND_OVERRIDE_SET(1)); udelay(1000); ath_reg_rmw_clear(RST_RESET2_ADDRESS, RST_RESET2_USB_PHY2_RESET_SET(1)); udelay(1000); ath_reg_rmw_clear(RST_RESET2_ADDRESS, RST_RESET2_USB_PHY2_ARESET_SET(1)); udelay(1000); ath_reg_rmw_clear(RST_RESET2_ADDRESS, RST_RESET2_USB_HOST2_RESET_SET(1)); udelay(1000); ath_reg_rmw_clear(RST_RESET2_ADDRESS, RST_RESET2_USB_PHY2_PLL_PWD_EXT_SET(1)); udelay(10); ath_reg_rmw_set(RST_RESET2_ADDRESS, RST_RESET2_USB2_EXT_PWR_SEQ_SET(1)); udelay(10); }
int __init ar7240_simple_config_init(void) { int req; /* restore factory default and system led */ dev_t dev; int rt; int current_wifi_value; int ar7240_gpio_major = gpio_major; int ar7240_gpio_minor = gpio_minor; init_timer(&rst_timer); rst_timer.function = check_rst; /* config gpio 11, 12, 14, 15, 16, 17 as normal gpio function */ /* gpio11 */ ath_reg_rmw_clear(ATH_GPIO_OUT_FUNCTION2, 0xff<<24); /* gpio12 */ ath_reg_rmw_clear(ATH_GPIO_OUT_FUNCTION3, 0xff<<0); /* gpio14 */ ath_reg_rmw_clear(ATH_GPIO_OUT_FUNCTION3, 0xff<<16); /* gpio15 */ ath_reg_rmw_clear(ATH_GPIO_OUT_FUNCTION3, 0xff<<24); /* gpio16 */ ath_reg_rmw_clear(ATH_GPIO_OUT_FUNCTION4, 0xff<<0); /* gpio17 */ ath_reg_rmw_clear(ATH_GPIO_OUT_FUNCTION4, 0xff<<8); #ifndef CONFIG_MUX_RESET_WPS_BUTTON /* This is NECESSARY, lsz 090109 */ ath_gpio_config_input(WPS_BUTTON_GPIO); /* configure JUMPSTART_GPIO as level triggered interrupt */ ath_gpio_config_int (WPS_BUTTON_GPIO, INT_TYPE_LEVEL, INT_POL_ACTIVE_LOW); req = request_irq (ATH_GPIO_IRQn(WPS_BUTTON_GPIO), wpsStart_irq, 0, "SW_WPSSTART", NULL); if (req != 0) { printk (KERN_ERR "unable to request IRQ for SWWPSSTART GPIO (error %d)\n", req); } #endif create_simple_config_led_proc_entry (); ath_gpio_config_input(RST_DFT_GPIO); /* configure GPIO RST_DFT_GPIO as level triggered interrupt */ ath_gpio_config_int (RST_DFT_GPIO, INT_TYPE_LEVEL, INT_POL_ACTIVE_LOW); rt = request_irq (ATH_GPIO_IRQn(RST_DFT_GPIO), rst_irq, 0, "RESTORE_FACTORY_DEFAULT", NULL); if (rt != 0) { printk (KERN_ERR "unable to request IRQ for RESTORE_FACTORY_DEFAULT GPIO (error %d)\n", rt); } /* wifi switch! */ ath_gpio_config_input(WIFI_RADIO_SW_GPIO); current_wifi_value = ath_reg_rd(ATH_GPIO_IN) & (1 << WIFI_RADIO_SW_GPIO); /* configure GPIO RST_DFT_GPIO as level triggered interrupt */ if(current_wifi_value == 0) { ignore_wifibutton = 1; ath_gpio_config_int (WIFI_RADIO_SW_GPIO, INT_TYPE_LEVEL, INT_POL_ACTIVE_LOW); } else { ignore_wifibutton =0; ath_gpio_config_int (WIFI_RADIO_SW_GPIO, INT_TYPE_LEVEL, INT_POL_ACTIVE_HIGH); } req = request_irq (ATH_GPIO_IRQn(WIFI_RADIO_SW_GPIO), wifi_sw_irq, 0, "WIFI_RADIO_SWITCH", NULL); if (req != 0) { printk (KERN_ERR "unable to request IRQ for WIFI_RADIO_SWITCH GPIO (error %d)\n", req); } if (ar7240_gpio_major) { dev = MKDEV(ar7240_gpio_major, ar7240_gpio_minor); rt = register_chrdev_region(dev, 1, "ar7240_gpio_chrdev"); } else { rt = alloc_chrdev_region(&dev, ar7240_gpio_minor, 1, "ar7240_gpio_chrdev"); ar7240_gpio_major = MAJOR(dev); } if (rt < 0) { printk(KERN_WARNING "ar7240_gpio_chrdev : can`t get major %d\n", ar7240_gpio_major); return rt; } cdev_init (&gpio_device_cdev, &gpio_device_op); rt = cdev_add(&gpio_device_cdev, dev, 1); if (rt < 0) printk(KERN_NOTICE "Error %d adding ar7240_gpio_chrdev ", rt); #ifdef AP_USB_LED_GPIO ath_gpio_config_output(AP_USB_LED_GPIO); #endif #ifdef AP_USB_1_LED_GPIO ath_gpio_config_output(AP_USB_1_LED_GPIO); #endif ath_gpio_config_output(SYS_LED_GPIO); /* for USB 3G by lyj, 31Aug11 */ #ifdef USB_POWER_SW_GPIO ath_gpio_config_output(USB_POWER_SW_GPIO); #endif #ifdef USB_1_POWER_SW_GPIO ath_gpio_config_output(USB_1_POWER_SW_GPIO); #endif /* s27 will use the gpio 18 19 as ethernet led */ #ifdef CONFIG_SUPPORT_S17 /* GPIO18-19 by lyj, 27Sep11 */ ath_reg_rmw_clear(ATH_GPIO_OUT_FUNCTION4, 0xff<<16); ath_reg_rmw_clear(ATH_GPIO_OUT_FUNCTION4, 0xff<<24); /* config GPIO18-19 as output by lyj, 27Sep11 */ ath_gpio_config_output(18); ath_gpio_config_output(19); /* set GPIO18-19, for AR9344 art (LNA) by lyj, 27Sep11 */ ath_reg_rmw_set(ATH_GPIO_OUT_FUNCTION4, 0x2f2e0000); #endif ath_gpio_out_val(SYS_LED_GPIO, SYS_LED_OFF); #ifdef AP_USB_LED_GPIO ath_gpio_out_val(AP_USB_LED_GPIO, USB_LED_OFF); #endif #ifdef AP_USB_1_LED_GPIO ath_gpio_out_val(AP_USB_1_LED_GPIO, USB_1_LED_OFF); #endif ath_gpio_out_val (TRICOLOR_LED_GREEN_PIN, OFF); /* for USB 3G by lyj, 31Aug11 */ #ifdef USB_POWER_SW_GPIO ath_gpio_out_val(USB_POWER_SW_GPIO, USB_POWER_ON); #endif #ifdef USB_1_POWER_SW_GPIO ath_gpio_out_val(USB_1_POWER_SW_GPIO, USB_1_POWER_ON); #endif return 0; }
void uart_gpio_init_qca956x(void) { #ifdef CONFIG_MACH_QCA956x #if defined(UART_RX20_TX22) val = (ath_reg_rd(GPIO_OE_ADDRESS) & (~0x400000)); ath_reg_wr(GPIO_OE_ADDRESS, val); ath_reg_rmw_clear(GPIO_OUT_FUNCTION5_ADDRESS, GPIO_OUT_FUNCTION5_ENABLE_GPIO_22_MASK); ath_reg_rmw_set(GPIO_OUT_FUNCTION5_ADDRESS, GPIO_OUT_FUNCTION5_ENABLE_GPIO_22_SET(0x16)); ath_reg_rmw_clear(GPIO_IN_ENABLE0_ADDRESS, GPIO_IN_ENABLE0_UART_SIN_MASK); ath_reg_rmw_set(GPIO_IN_ENABLE0_ADDRESS, GPIO_IN_ENABLE0_UART_SIN_SET(0x14)); #elif defined(UART_RX18_TX22) val = (ath_reg_rd(GPIO_OE_ADDRESS) & (~0x400000)) | 0x40000; ath_reg_wr(GPIO_OE_ADDRESS, val); ath_reg_rmw_clear(GPIO_OUT_FUNCTION5_ADDRESS, GPIO_OUT_FUNCTION5_ENABLE_GPIO_22_MASK); ath_reg_rmw_set(GPIO_OUT_FUNCTION5_ADDRESS, GPIO_OUT_FUNCTION5_ENABLE_GPIO_22_SET(0x16)); ath_reg_rmw_clear(GPIO_IN_ENABLE0_ADDRESS, GPIO_IN_ENABLE0_UART_SIN_MASK); ath_reg_rmw_set(GPIO_IN_ENABLE0_ADDRESS, GPIO_IN_ENABLE0_UART_SIN_SET(0x12)); #elif defined(UART_RX18_TX20) val = (ath_reg_rd(GPIO_OE_ADDRESS) & (~0x100000)) | 0x40000; ath_reg_wr(GPIO_OE_ADDRESS, val); val = ath_reg_rd(GPIO_OUT_ADDRESS) | 0xeffff6; ath_reg_wr(GPIO_OUT_ADDRESS, val); ath_reg_rmw_clear(GPIO_OUT_FUNCTION5_ADDRESS, GPIO_OUT_FUNCTION5_ENABLE_GPIO_20_MASK); ath_reg_rmw_set(GPIO_OUT_FUNCTION5_ADDRESS, GPIO_OUT_FUNCTION5_ENABLE_GPIO_20_SET(0x16)); ath_reg_rmw_clear(GPIO_IN_ENABLE0_ADDRESS, GPIO_IN_ENABLE0_UART_SIN_MASK); ath_reg_rmw_set(GPIO_IN_ENABLE0_ADDRESS, GPIO_IN_ENABLE0_UART_SIN_SET(0x12)); #elif defined(UART_RX24_TX20) // Turn off LED before XLNA swap to GPO val = ath_reg_rd(GPIO_OUT_ADDRESS) | 0xaffff6; ath_reg_wr(GPIO_OUT_ADDRESS, val); //Switch GPI and GPO and XPA, XLNA ath_reg_wr(GPIO_FUNCTION_ADDRESS, 0x8000); val = (ath_reg_rd(GPIO_OE_ADDRESS) & (~0x100000)) | 0x1000000; ath_reg_wr(GPIO_OE_ADDRESS, val); ath_reg_rmw_set(GPIO_OUT_FUNCTION5_ADDRESS, GPIO_OUT_FUNCTION5_ENABLE_GPIO_20_SET(0x16)); ath_reg_rmw_clear(GPIO_IN_ENABLE0_ADDRESS, GPIO_IN_ENABLE0_UART_SIN_SET(0xff)); ath_reg_rmw_set(GPIO_IN_ENABLE0_ADDRESS, GPIO_IN_ENABLE0_UART_SIN_SET(0x18)); #elif defined(TEST_BOARD_UART) //Switch GPI and GPO and XPA1, ANTC ath_reg_wr(GPIO_FUNCTION_ADDRESS, 0xc000); val = ath_reg_rd(GPIO_OE_ADDRESS) & (~0x2000); ath_reg_wr(GPIO_OE_ADDRESS, val); ath_reg_rmw_clear(GPIO_OUT_FUNCTION3_ADDRESS, GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_MASK); ath_reg_rmw_set(GPIO_OUT_FUNCTION3_ADDRESS, GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_SET(0x16)); ath_reg_rmw_clear(GPIO_IN_ENABLE0_ADDRESS, GPIO_IN_ENABLE0_UART_SIN_SET(0xff)); ath_reg_rmw_set(GPIO_IN_ENABLE0_ADDRESS, GPIO_IN_ENABLE0_UART_SIN_SET(0x17)); #else val = (ath_reg_rd(GPIO_OE_ADDRESS) & (~0x100000)) | 0x80000; ath_reg_wr(GPIO_OE_ADDRESS, val); ath_reg_rmw_set(GPIO_OUT_FUNCTION5_ADDRESS, GPIO_OUT_FUNCTION5_ENABLE_GPIO_20_SET(0x16)); ath_reg_rmw_clear(GPIO_IN_ENABLE0_ADDRESS, GPIO_IN_ENABLE0_UART_SIN_SET(0xff)); ath_reg_rmw_set(GPIO_IN_ENABLE0_ADDRESS, GPIO_IN_ENABLE0_UART_SIN_SET(0x13)); #endif val = ath_reg_rd(GPIO_OUT_ADDRESS) | 0xaffff6; ath_reg_wr(GPIO_OUT_ADDRESS, val); val = ath_reg_rd(GPIO_SPARE_ADDRESS); ath_reg_wr(GPIO_SPARE_ADDRESS, (val | 0x8402)); #endif }
/* * We want a 1:1 mapping between PCI and DDR for inbound and outbound. * The PCI<---AHB decoding works as follows: * * 8 registers in the DDR unit provide software configurable 32 bit offsets * for each of the eight 16MB PCI windows in the 128MB. The offsets will be * added to any address in the 16MB segment before being sent to the PCI unit. * * Essentially for any AHB address generated by the CPU, * 1. the MSB four bits are stripped off, [31:28], * 2. Bit 27 is used to decide between the lower 128Mb (PCI) or the rest of * the AHB space * 3. Bits 26:24 are used to access one of the 8 window registers and are * masked off. * 4. If it is a PCI address, then the WINDOW offset in the WINDOW register * corresponding to the next 3 bits (bit 26:24) is ADDED to the address, * to generate the address to PCI unit. * * eg. CPU address = 0x100000ff * window 0 offset = 0x10000000 * This points to lowermost 16MB window in PCI space. * So the resulting address would be 0x000000ff+0x10000000 * = 0x100000ff * * eg2. CPU address = 0x120000ff * WINDOW 2 offset = 0x12000000 * resulting address would be 0x000000ff+0x12000000 * = 0x120000ff * * There is no translation for inbound access (PCI device as a master) */ static int __init ath_pcibios_init(void) { uint32_t cmd; #ifdef CONFIG_MACH_AR934x if (is_ar9341()) { return 0; } #endif /* * Check if the WLAN PCI-E H/W is present, If the * WLAN H/W is not present, skip the PCI * initialization code and just return. */ if (((ath_reg_rd(ATH_PCI_LCL_RESET)) & 0x1) == 0x0) { printk("***** Warning *****: PCIe WLAN H/W not found !!!\n"); return 0; } if ((is_ar7241() || is_ar7242())) ath_reg_wr(ATH_PCI_LCL_APP, (ath_reg_rd(ATH_PCI_LCL_APP) | (0x1 << 16))); #ifdef CONFIG_PERICOM ath_reg_wr(0xb80f0000, 0x0ffc1); // Address Translation disabled ath_reg_wr(0x180f0040, 0); // Enable Type 0 ath_reg_rd(0x14000000); // Reading the Config space of Upstream port of Switch ath_reg_wr(0x1400003c, 0x400000); // Assert Reset to the Downstream ports ath_reg_wr(0x1400003c, 0x0); // Deassert Reset ath_reg_wr(0x14000004, 0x106); ath_reg_wr(0x14000018, 0x070504); // Program the Primary Bus, Sec Bus and Subordinate Bus ath_reg_wr(0x14000020, 0x1ff01000); // Memory Base and Limit ath_reg_wr(0x14000024, 0x1ff01000); // Prefetch Memory Base and Limit ath_reg_wr(0x140000b4, 0x0200010a); // Enable Round robin priority on the ports ath_reg_wr(0x180f0040, 1); // Enable Type 1 // Configure the Pericom Switch's Downstream Port0 using Type1 Configuration ath_reg_rd(0x15080000); // Reading the Config space of Downstream port0 of Switch ath_reg_wr(0x15080004, 0x106); // Command register ath_reg_wr(0x15080018, 0x060605); // Program the pri bus, sec bus and subordinate bus ath_reg_wr(0x15080020, 0x11f01000); // Memory base and limit ath_reg_wr(0x15080024, 0x11f01000); // Configure the Pericom Switch's Downstream Port1 using Type1 Configuration ath_reg_rd(0x15100000); // Reading the Config space of Downstream port1 of Switch ath_reg_wr(0x15100004, 0x106); ath_reg_wr(0x15100018, 0x070705); ath_reg_wr(0x15100020, 0x13f01200); ath_reg_wr(0x15100024, 0x13f01200); ath_reg_wr(0xb80f0000, 0x1ffc1); // Address Translation enabled #endif /* CONFIG_PERICOM */ printk("PCI init:%s\n", __func__); #ifndef CONFIG_PCI_INIT_IN_MONITOR cmd = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK; printk("%s(%d): PCI CMD write: 0x%x\n", __func__, __LINE__, cmd); ath_local_write_config(PCI_COMMAND, 4, cmd); /* * clear any lingering errors and register core error IRQ */ #if 0 ath_check_error(0); #endif # if !defined(CONFIG_PERICOM) ath_pci_ops.write(NULL, 0, PCI_COMMAND, 4, cmd); # endif /* CONFIG_PERICOM */ #endif #ifdef CONFIG_PERICOM #define ath_udelay(us) do { \ extern uint32_t ath_cpu_freq; \ volatile register int N = (ath_cpu_freq / 1000000) * (us); \ while (--N > 0); \ } while(0) /* For Pericom -> Merlin link availability */ ath_udelay(600); cmd = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SERR; printk("%s: cmd = 0x%x\n", __func__, cmd); ath_pci_ops.write(2, 0, PCI_COMMAND, 4, cmd); ath_pci_ops.write(1, 0, PCI_COMMAND, 4, cmd); register_pci_controller(&ath_pci_controller1); register_pci_controller(&ath_pci_controller2); #else #if ATH_LOW_POWER_ENABLE // Enable L0 & L1 ASPM Support ath_reg_rmw_set(ATH_PCIE_RC_ASPM_SUPPORT, ATH_PCIE_RC_SUPP_L0 | ATH_PCIE_RC_SUPP_L1); // Enable L0 & L1 ath_reg_rmw_set(ATH_PCIE_RC_ASPM_ENABLE, ATH_PCIE_RC_EN_L0 | ATH_PCIE_RC_EN_L1); #endif register_pci_controller(&ath_pci_controller); #endif /* CONFIG_PERICOM */ return 0; }
int pci_init_board (void) { #ifdef CONFIG_ATH_EMULATION printf("--- Skipping %s for emulation\n", __func__); #else uint32_t cmd; // common for rc1 and rc2 ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MAX_ADDRESS, PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_SET(1) | PCIE_PLL_DITHER_DIV_MAX_USE_MAX_SET(1) | PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_SET(0x14) | PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_SET(0x3ff)); ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MIN_ADDRESS, PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_SET(0x14)); ath_reg_wr_nf(PCIE_PLL_CONFIG_ADDRESS, PCIE_PLL_CONFIG_REFDIV_SET(1) | PCIE_PLL_CONFIG_BYPASS_SET(1) | PCIE_PLL_CONFIG_PLLPWD_SET(1)); udelay(10000); ath_reg_rmw_clear(PCIE_PLL_CONFIG_ADDRESS, PCIE_PLL_CONFIG_PLLPWD_SET(1)); udelay(1000); ath_reg_rmw_clear(PCIE_PLL_CONFIG_ADDRESS, PCIE_PLL_CONFIG_BYPASS_SET(1)); udelay(1000); if (!(ath_reg_rd(RST_BOOTSTRAP_ADDRESS) & RST_BOOTSTRAP_PCIE_RC_EP_SELECT_MASK)) { pci_rc2_init_board(); return 0; } ath_reg_rmw_set(RST_RESET_ADDRESS, RST_RESET_PCIE_PHY_RESET_SET(1)); udelay(10000); ath_reg_rmw_set(RST_RESET_ADDRESS, RST_RESET_PCIE_RESET_SET(1)); udelay(10000); ath_reg_rmw_clear(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY_SET(1)); udelay(10000); ath_reg_wr_nf(PCIE_RESET_ADDRESS, 0); // Put endpoint in reset udelay(100000); ath_reg_rmw_set(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY_SET(1)); udelay(10000); ath_reg_rmw_clear(RST_RESET_ADDRESS, RST_RESET_PCIE_PHY_RESET_SET(1)); udelay(10000); ath_reg_rmw_clear(RST_RESET_ADDRESS, RST_RESET_PCIE_RESET_SET(1)); udelay(10000); ath_reg_wr_nf(PCIE_APP_ADDRESS, PCIE_APP_PCIE_BAR_MSN_SET(1) | PCIE_APP_CFG_BE_SET(0xf) | PCIE_APP_SLV_RESP_ERR_MAP_SET(0x3f) | PCIE_APP_LTSSM_ENABLE_SET(1)); cmd = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK; ath_local_write_config(PCI_COMMAND, 4, cmd); ath_local_write_config(0x20, 4, 0x1ff01000); ath_local_write_config(0x24, 4, 0x1ff01000); ath_reg_wr_nf(PCIE_RESET_ADDRESS, 4); // Pull endpoint out of reset udelay(100000); /* training reset */ ath_reg_rmw_set(PCIE_APP_ADDRESS, PCIE_APP_INIT_RST_SET(1)); udelay(1000); /* * Check if the WLAN PCI-E H/W is present, If the * WLAN H/W is not present, skip the PCI platform * initialization code and return */ if (((ath_reg_rd(PCIE_RESET_ADDRESS)) & 0x1) == 0x0) { printf("*** Warning *** : PCIe WLAN Module not found !!!\n"); } pci_rc2_init_board(); #endif /* CONFIG_ATH_EMULATION */ return 0; }
PCI_INIT_RET_TYPE pci_init_board (void) { #ifdef CONFIG_ATH_EMULATION prmsg("--- Skipping %s for emulation\n", __func__); #else uint32_t cmd; if (is_drqfn() && !is_qca953x()) { /* * Dont enable PCIe in DRQFN package as it has some issues * related to PCIe */ PCI_INIT_RETURN; } #if defined(CONFIG_MACH_QCA953x) if (ath_reg_rd(RST_BOOTSTRAP_ADDRESS) & RST_BOOTSTRAP_TESTROM_ENABLE_MASK) { ath_reg_rmw_clear(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY_SET(1)); ath_reg_wr(PCIE_PHY_REG_1_ADDRESS, PCIE_PHY_REG_1_RESET_1); ath_reg_wr(PCIE_PHY_REG_3_ADDRESS, PCIE_PHY_REG_3_RESET_1); ath_reg_rmw_set(PCIE_PWR_MGMT_ADDRESS, PCIE_PWR_MGMT_ASSERT_CLKREQN_SET(1)); ath_reg_rmw_set(PCIE_PLL_CONFIG_ADDRESS, PCIE_PLL_CONFIG_PLLPWD_SET(1)); ath_reg_rmw_set(RST_RESET_ADDRESS, RST_RESET_PCIE_RESET_SET(1)); ath_reg_rmw_set(RST_RESET_ADDRESS, RST_RESET_PCIE_PHY_RESET_SET(1)); ath_reg_rmw_clear(RST_CLKGAT_EN_ADDRESS, RST_CLKGAT_EN_PCIE_RC_SET(1)); PCI_INIT_RETURN; } else { /* Honeybee -The PCIe reference clock frequency is being changed to vary from 99.968MHz to 99.999MHz using SS modulation */ ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MAX_ADDRESS, PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_SET(0x1) | PCIE_PLL_DITHER_DIV_MAX_USE_MAX_SET(0x1) | PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_SET(0x17) | PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_SET(0x3fff)); ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MIN_ADDRESS, PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_SET(0x3f84)| PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_SET(0x17)); } #else #if defined(CONFIG_MACH_QCA956x) ath_reg_rmw_set(PCIE_PHY_REG_1_ADDRESS, PCIE_PHY_REG_1_S_SET(PCIE_PHY_REG_1_S_RESET)); ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MAX_ADDRESS, PCIE_PLL_DITHER_DIV_MAX_USE_MAX_SET(0x1) | PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_SET(0x17) | PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_SET(0x3fff)); ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MIN_ADDRESS, PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_SET(0x3f84) | PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_SET(0x17)); #else // common for rc1 and rc2 ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MAX_ADDRESS, PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_SET(0x1) | PCIE_PLL_DITHER_DIV_MAX_USE_MAX_SET(0x1) | PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_SET(0x14) | PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_SET(0x3ff)); ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MIN_ADDRESS, PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_SET(0x14)); #endif #endif ath_reg_wr_nf(PCIE_PLL_CONFIG_ADDRESS, PCIE_PLL_CONFIG_REFDIV_SET(1) | PCIE_PLL_CONFIG_BYPASS_SET(1) | PCIE_PLL_CONFIG_PLLPWD_SET(1)); udelay(10000); ath_reg_rmw_clear(PCIE_PLL_CONFIG_ADDRESS, PCIE_PLL_CONFIG_PLLPWD_SET(1)); udelay(1000); ath_reg_rmw_clear(PCIE_PLL_CONFIG_ADDRESS, PCIE_PLL_CONFIG_BYPASS_SET(1)); udelay(1000); #if !defined(CONFIG_MACH_QCA956x) #ifdef PCIE2_APP_ADDRESS if (!(ath_reg_rd(RST_BOOTSTRAP_ADDRESS) & RST_BOOTSTRAP_PCIE_RC_EP_SELECT_MASK)) { pci_rc2_init_board(); return; } #endif ath_reg_rmw_set(RST_RESET_ADDRESS, RST_RESET_PCIE_PHY_RESET_SET(1)); udelay(10000); ath_reg_rmw_set(RST_RESET_ADDRESS, RST_RESET_PCIE_RESET_SET(1)); udelay(10000); #ifdef PCIE2_APP_ADDRESS ath_reg_rmw_clear(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY_SET(1)); udelay(10000); #endif ath_reg_wr_nf(PCIE_RESET_ADDRESS, 0); // Put endpoint in reset udelay(100000); #ifdef PCIE2_APP_ADDRESS ath_reg_rmw_set(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY_SET(1)); udelay(10000); #endif ath_reg_rmw_clear(RST_RESET_ADDRESS, RST_RESET_PCIE_PHY_RESET_SET(1)); udelay(10000); ath_reg_rmw_clear(RST_RESET_ADDRESS, RST_RESET_PCIE_RESET_SET(1)); udelay(10000); ath_reg_wr_nf(PCIE_APP_ADDRESS, PCIE_APP_PCIE_BAR_MSN_SET(1) | PCIE_APP_CFG_BE_SET(0xf) | PCIE_APP_SLV_RESP_ERR_MAP_SET(0x3f) | PCIE_APP_LTSSM_ENABLE_SET(1)); cmd = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK; ath_local_write_config(PCI_COMMAND, 4, cmd); ath_local_write_config(0x20, 4, 0x1ff01000); ath_local_write_config(0x24, 4, 0x1ff01000); ath_reg_wr_nf(PCIE_RESET_ADDRESS, 4); // Pull endpoint out of reset udelay(100000); /* * Check if the WLAN PCI-E H/W is present, If the * WLAN H/W is not present, skip the PCI platform * initialization code and return */ if (((ath_reg_rd(PCIE_RESET_ADDRESS)) & 0x1) == 0x0) { prmsg("*** Warning *** : PCIe WLAN Module not found !!!\n"); } #endif #ifdef PCIE2_APP_ADDRESS pci_rc2_init_board(); #endif #ifndef COMPRESSED_UBOOT /* * Now, configure for u-boot tools */ hose.first_busno = 0; hose.last_busno = 0xff; /* System space */ pci_set_region( &hose.regions[0], 0x80000000, 0x00000000, 32 * 1024 * 1024, PCI_REGION_MEM | PCI_REGION_MEMORY); /* PCI memory space */ pci_set_region( &hose.regions[1], 0x10000000, 0x10000000, 128 * 1024 * 1024, PCI_REGION_MEM); hose.region_count = 2; pci_register_hose(&hose); pci_set_ops( &hose, pci_hose_read_config_byte_via_dword, pci_hose_read_config_word_via_dword, ath_pci_read_config, pci_hose_write_config_byte_via_dword, pci_hose_write_config_word_via_dword, ath_pci_write_config); #endif plat_dev_init(); #endif /* CONFIG_ATH_EMULATION */ PCI_INIT_RETURN; }
int do_frag_hw(ath_hwcs_node_info_t *rx_entries, ath_hwcs_node_info_t *tx_entry, int num) { int i; volatile ath_hwcs_desc_t *desc = NULL, *firstDesc = NULL; volatile ath_hwcs_desc_t *tx_desc = NULL; dma_addr_t tx_handle; dma_addr_t rx_handles[512]; tx_desc = (ath_hwcs_desc_t *)dma_pool_alloc(dmapool, GFP_KERNEL, &tx_handle); tx_desc->buf = tx_entry->buf; if (num != 0) { tx_desc->info.status = (0x0 | ATH_HWCS_TX_SOF_MASK | ATH_HWCS_TX_EOF_MASK | ATH_HWCS_TYPE_WITH_CP); } else { #ifdef CONFIG_ATH_HWCS_INT tx_desc->info.status = (0x0 | ATH_HWCS_TX_SOF_MASK | ATH_HWCS_TX_EOF_MASK | ATH_HWCS_TYPE_CSUM_ONLY | ATH_HWCS_INTR_ENABLE); ath_reg_rmw_set(ATH_HWCS_IMASK, ATH_HWCS_TX_INTR_MASK); #else tx_desc->info.status = (0x0 | ATH_HWCS_TX_SOF_MASK | ATH_HWCS_TX_EOF_MASK | ATH_HWCS_TYPE_CSUM_ONLY); #endif } tx_desc->info.control.pktSize = tx_entry->len; tx_desc->next = (ath_hwcs_desc_t *)tx_desc; for(i=0; i<num; i++) { if(NULL == desc) { desc = (ath_hwcs_desc_t *)dma_pool_alloc(dmapool, GFP_KERNEL, &rx_handles[i]); firstDesc = desc; } else { desc->next = (ath_hwcs_desc_t *)dma_pool_alloc(dmapool, GFP_KERNEL, &rx_handles[i]); desc = desc->next; } desc->buf = rx_entries[i].buf; desc->info.status = (0x0 | ATH_HWCS_PKT_VOID); desc->info.control.pktSize = rx_entries[i].len; } if (num != 0) { desc->next = (ath_hwcs_desc_t *)firstDesc; #ifdef CONFIG_ATH_HWCS_INT ath_reg_rmw_set(ATH_HWCS_IMASK, ATH_HWCS_RX_INTR_MASK); desc->info.status |= ATH_HWCS_INTR_ENABLE; #endif ath_reg_wr(ATH_HWCS_DMARX_DESC, (unsigned int)rx_handles[0]); ath_reg_wr(ATH_HWCS_DMARX_CONTROL, ATH_HWCS_DMARX_ENABLE); } ath_reg_wr(ATH_HWCS_DMATX_DESC0, (unsigned int)tx_handle); ath_reg_wr(ATH_HWCS_DMATX_CONTROL0, ATH_HWCS_DMATX_ENABLE); #ifdef CONFIG_ATH_HWCS_INT if(num == 0) wait_event_interruptible(wq, (check_pkt_void(tx_desc) == 1)); #else while ((check_pkt_void(tx_desc)) == 0); #endif if (num != 0) { #ifdef CONFIG_ATH_HWCS_INT wait_event_interruptible(wq, (check_pkt_void(desc) == 0)); #endif desc = firstDesc; for(i=0; i<num; i++) { #ifndef CONFIG_ATH_HWCS_INT while ((check_pkt_void(desc)) != 0); #endif rx_entries[i].checksum = (desc->info.control.pktSize & 0xffff); rx_entries[i].actual = (desc->status_only & 0x7ffff); #if 0 if(rx_entries[i].actual < rx_entries[i].len) { retval = -1; break; } #endif firstDesc = desc; desc = desc->next; dma_pool_free(dmapool, (void *)firstDesc, rx_handles[i]); } } tx_entry->checksum = (tx_desc->info.control.pktSize & 0xffff); tx_entry->actual = (tx_desc->status_only & 0x7ffff); dma_pool_free(dmapool, (void *)tx_desc, tx_handle); return 0; }
void pci_rc2_init_board (void) { #if defined(CONFIG_MACH_QCA956x) ath_reg_rmw_clear(GPIO_OE_ADDRESS, 0x1); udelay(10000); ath_reg_rmw_set(GPIO_OUT_FUNCTION0_ADDRESS, GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_SET(0x73)); udelay(10000); ath_reg_rmw_set(RST_RESET_ADDRESS,RST_RESET_PCIE_PHY_RESET_SET(1) | RST_RESET_PCIE_RESET_SET(1)); udelay(10000); ath_reg_rmw_clear(RST_RESET_ADDRESS,RST_RESET_PCIE_PHY_RESET_SET(1) | RST_RESET_PCIE_RESET_SET(1)); udelay(10000); ath_reg_rmw_set(RST_RESET2_ADDRESS,RST_RESET_PCIE_PHY_RESET_SET(1) | RST_RESET_PCIE_RESET_SET(1)); udelay(10000); ath_reg_rmw_clear(RST_RESET2_ADDRESS,RST_RESET_PCIE_PHY_RESET_SET(1) | RST_RESET_PCIE_RESET_SET(1)); udelay(10000); ath_reg_wr(PCIE2_RESET_ADDRESS,PCIE2_RESET_EP_RESET_L_SET(1)); udelay(10000); ath_reg_wr(ATH_PCI_CRP_WRDATA,0x6); udelay(10000); ath_reg_wr(PCIE_APP_ADDRESS,PCIE_APP_LTSSM_ENABLE_SET(1) | PCIE_APP_SLV_RESP_ERR_MAP_SET(0x3f) | PCIE_APP_CFG_BE_SET(0xf) | PCIE_APP_PCIE_BAR_MSN_SET(1)); udelay(10000); ath_reg_wr(PCIE_INT_MASK_ADDRESS,PCIE_INT_MASK_CORR_ERR_SET(1) | PCIE_INT_MASK_NONFATAL_ERR_SET(1) | PCIE_INT_MASK_FATAL_ERR_SET(1) | PCIE_INT_MASK_GM_COMP_LOOKUP_ERR_SET(1) | PCIE_INT_MASK_RADMX_COMP_LOOKUP_ERR_SET(1) | PCIE_INT_MASK_INTA_SET(1) | PCIE_INT_MASK_INTB_SET(1) | PCIE_INT_MASK_INTC_SET(1) | PCIE_INT_MASK_INTD_SET(1) | PCIE_INT_MASK_MSI_SET(1) | PCIE_INT_MASK_MSI_ERR_SET(1) | PCIE_INT_MASK_AER_INT_SET(1) | PCIE_INT_MASK_AER_MSI_SET(1) | PCIE_INT_MASK_SYS_ERR_SET(1) | PCIE_INT_MASK_INTAL_SET(1) | PCIE_INT_MASK_INTBL_SET(1) | PCIE_INT_MASK_INTCL_SET(1) | PCIE_INT_MASK_INTDL_SET(1)); udelay(10000); ath_local_write_config_rc2(0x70c, 4, 0x1b403200); udelay(10000); ath_reg_wr(PCIE_DEBUG_ADDRESS,PCIE_DEBUG_BYTESWAP_SET(1)); udelay(10000); ath_reg_rmw_set(XTAL2_SEC_ADDRESS, XTAL2_SEC_SPARE_SET(0xc)); udelay(10000); ath_reg_rmw_clear(PCIe_DPLL2_ADDRESS, PCIe_DPLL2_KI_SET(0x3) | PCIe_DPLL2_KD_SET(0xF)); udelay(10000); ath_reg_rmw_set(PCIe_DPLL2_ADDRESS, PCIe_DPLL2_KD_SET(0x4)); udelay(10000); #else uint32_t cmd; ath_reg_rmw_set(RST_RESET2_ADDRESS, RST_RESET2_PCIE2_PHY_RESET_SET(1)); udelay(10000); ath_reg_rmw_set(RST_RESET2_ADDRESS, RST_RESET2_PCIE2_RESET_SET(1)); udelay(10000); ath_reg_rmw_clear(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY2_SET(1)); udelay(10000); ath_reg_wr_nf(PCIE2_RESET_ADDRESS, 0); // Put endpoint in reset udelay(100000); ath_reg_rmw_set(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY2_SET(1)); udelay(10000); ath_reg_rmw_clear(RST_RESET2_ADDRESS, RST_RESET_PCIE_PHY_RESET_SET(1)); udelay(10000); ath_reg_rmw_clear(RST_RESET2_ADDRESS, RST_RESET_PCIE_RESET_SET(1)); udelay(10000); ath_reg_wr_nf(PCIE2_APP_ADDRESS, PCIE2_APP_PCIE2_BAR_MSN_SET(1) | PCIE2_APP_CFG_BE_SET(0xf) | PCIE2_APP_SLV_RESP_ERR_MAP_SET(0x3f) | PCIE2_APP_LTSSM_ENABLE_SET(1)); cmd = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK; ath_local_write_config_rc2(PCI_COMMAND, 4, cmd); ath_local_write_config_rc2(0x20, 4, 0x1ff01000); ath_local_write_config_rc2(0x24, 4, 0x1ff01000); ath_reg_wr_nf(PCIE2_RESET_ADDRESS, 4); // Pull endpoint out of reset udelay(100000); #endif /* * Check if the WLAN PCI-E H/W is present, If the * WLAN H/W is not present, skip the PCI platform * initialization code and return */ if (((ath_reg_rd(PCIE2_RESET_ADDRESS)) & 0x1) == 0x0) { prmsg("*** Warning *** : PCIe WLAN Module not found !!!\n"); return; } }
static void ath_gpio_intr_enable(unsigned int irq) { ath_reg_rmw_set(ATH_GPIO_INT_MASK, (1 << (irq - ATH_GPIO_IRQ_BASE))); }