/*
* Handle an AST for the current process.
*/
void
ast(void)
{
struct cpu_info *ci = curcpu();
struct proc *p = ci->ci_curproc;
p->p_md.md_astpending = 0;
atomic_inc_int(&uvmexp.softs);
mi_ast(p, ci->ci_want_resched);
userret(p);
}
/*
* Process pending software interrupts on the specified queue.
*
* NOTE: We must already be at the correct interrupt priority level.
*/
void
softintr_dispatch(int si)
{
struct soft_intrq *siq = &soft_intrq[si];
struct soft_intrhand *sih;
for (;;) {
mtx_enter(&siq->siq_mtx);
sih = TAILQ_FIRST(&siq->siq_list);
if (sih == NULL) {
mtx_leave(&siq->siq_mtx);
break;
}
TAILQ_REMOVE(&siq->siq_list, sih, sih_list);
sih->sih_pending = 0;
atomic_inc_int(&uvmexp.softs);
mtx_leave(&siq->siq_mtx);
(*sih->sih_func)(sih->sih_arg);
}
}
void
vnet_start_desc(struct ifnet *ifp)
{
struct vnet_softc *sc = ifp->if_softc;
struct ldc_map *map = sc->sc_lm;
struct vnet_desc_msg dm;
struct mbuf *m;
paddr_t pa;
caddr_t buf;
u_int prod, count;
for (;;) {
IFQ_POLL(&ifp->if_snd, m);
if (m == NULL)
break;
count = sc->sc_tx_prod - sc->sc_tx_cons;
if (count >= (sc->sc_vd->vd_nentries - 1) ||
map->lm_count >= map->lm_nentries) {
ifp->if_flags |= IFF_OACTIVE;
return;
}
buf = pool_get(&sc->sc_pool, PR_NOWAIT|PR_ZERO);
if (buf == NULL) {
ifp->if_flags |= IFF_OACTIVE;
return;
}
m_copydata(m, 0, m->m_pkthdr.len, buf);
IFQ_DEQUEUE(&ifp->if_snd, m);
#if NBPFILTER > 0
/*
* If BPF is listening on this interface, let it see the
* packet before we commit it to the wire.
*/
if (ifp->if_bpf)
bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT);
#endif
pmap_extract(pmap_kernel(), (vaddr_t)buf, &pa);
KASSERT((pa & ~PAGE_MASK) == (pa & LDC_MTE_RA_MASK));
while (map->lm_slot[map->lm_next].entry != 0) {
map->lm_next++;
map->lm_next &= (map->lm_nentries - 1);
}
map->lm_slot[map->lm_next].entry = (pa & LDC_MTE_RA_MASK);
map->lm_slot[map->lm_next].entry |= LDC_MTE_CPR;
atomic_inc_int(&map->lm_count);
prod = sc->sc_tx_prod & (sc->sc_vd->vd_nentries - 1);
sc->sc_vsd[prod].vsd_map_idx = map->lm_next;
sc->sc_vsd[prod].vsd_buf = buf;
bzero(&dm, sizeof(dm));
dm.tag.type = VIO_TYPE_DATA;
dm.tag.stype = VIO_SUBTYPE_INFO;
dm.tag.stype_env = VIO_DESC_DATA;
dm.tag.sid = sc->sc_local_sid;
dm.seq_no = sc->sc_seq_no++;
dm.desc_handle = sc->sc_tx_prod;
dm.nbytes = max(m->m_pkthdr.len, 60);
dm.ncookies = 1;
dm.cookie[0].addr =
map->lm_next << PAGE_SHIFT | (pa & PAGE_MASK);
dm.cookie[0].size = 2048;
vnet_sendmsg(sc, &dm, sizeof(dm));
sc->sc_tx_prod++;
sc->sc_tx_prod &= (sc->sc_vd->vd_nentries - 1);
m_freem(m);
}
}
void
vnet_start(struct ifnet *ifp)
{
struct vnet_softc *sc = ifp->if_softc;
struct ldc_conn *lc = &sc->sc_lc;
struct ldc_map *map = sc->sc_lm;
struct mbuf *m;
paddr_t pa;
caddr_t buf;
uint64_t tx_head, tx_tail, tx_state;
u_int start, prod, count;
int err;
if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
return;
if (IFQ_IS_EMPTY(&ifp->if_snd))
return;
/*
* We cannot transmit packets until a VIO connection has been
* established.
*/
if (!ISSET(sc->sc_vio_state, VIO_RCV_RDX) ||
!ISSET(sc->sc_vio_state, VIO_ACK_RDX))
return;
/*
* Make sure there is room in the LDC transmit queue to send a
* DRING_DATA message.
*/
err = hv_ldc_tx_get_state(lc->lc_id, &tx_head, &tx_tail, &tx_state);
if (err != H_EOK)
return;
tx_tail += sizeof(struct ldc_pkt);
tx_tail &= ((lc->lc_txq->lq_nentries * sizeof(struct ldc_pkt)) - 1);
if (tx_tail == tx_head) {
ifp->if_flags |= IFF_OACTIVE;
return;
}
if (sc->sc_xfer_mode == VIO_DESC_MODE) {
vnet_start_desc(ifp);
return;
}
start = prod = sc->sc_tx_prod & (sc->sc_vd->vd_nentries - 1);
while (sc->sc_vd->vd_desc[prod].hdr.dstate == VIO_DESC_FREE) {
IFQ_POLL(&ifp->if_snd, m);
if (m == NULL)
break;
count = sc->sc_tx_prod - sc->sc_tx_cons;
if (count >= (sc->sc_vd->vd_nentries - 1) ||
map->lm_count >= map->lm_nentries) {
ifp->if_flags |= IFF_OACTIVE;
break;
}
buf = pool_get(&sc->sc_pool, PR_NOWAIT|PR_ZERO);
if (buf == NULL) {
ifp->if_flags |= IFF_OACTIVE;
break;
}
m_copydata(m, 0, m->m_pkthdr.len, buf + VNET_ETHER_ALIGN);
IFQ_DEQUEUE(&ifp->if_snd, m);
#if NBPFILTER > 0
/*
* If BPF is listening on this interface, let it see the
* packet before we commit it to the wire.
*/
if (ifp->if_bpf)
bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT);
#endif
pmap_extract(pmap_kernel(), (vaddr_t)buf, &pa);
KASSERT((pa & ~PAGE_MASK) == (pa & LDC_MTE_RA_MASK));
while (map->lm_slot[map->lm_next].entry != 0) {
map->lm_next++;
map->lm_next &= (map->lm_nentries - 1);
}
map->lm_slot[map->lm_next].entry = (pa & LDC_MTE_RA_MASK);
map->lm_slot[map->lm_next].entry |= LDC_MTE_CPR;
atomic_inc_int(&map->lm_count);
sc->sc_vd->vd_desc[prod].nbytes = max(m->m_pkthdr.len, 60);
sc->sc_vd->vd_desc[prod].ncookies = 1;
sc->sc_vd->vd_desc[prod].cookie[0].addr =
map->lm_next << PAGE_SHIFT | (pa & PAGE_MASK);
sc->sc_vd->vd_desc[prod].cookie[0].size = 2048;
membar_producer();
sc->sc_vd->vd_desc[prod].hdr.dstate = VIO_DESC_READY;
sc->sc_vsd[prod].vsd_map_idx = map->lm_next;
sc->sc_vsd[prod].vsd_buf = buf;
sc->sc_tx_prod++;
prod = sc->sc_tx_prod & (sc->sc_vd->vd_nentries - 1);
m_freem(m);
}
membar_producer();
if (start != prod && sc->sc_peer_state != VIO_DP_ACTIVE) {
vnet_send_dring_data(sc, start);
ifp->if_timer = 5;
}
}
/*
* Handle a single exception.
*/
void
itsa(struct trapframe *trapframe, struct cpu_info *ci, struct proc *p,
int type)
{
int i;
unsigned ucode = 0;
vm_prot_t ftype;
extern vaddr_t onfault_table[];
int onfault;
int typ = 0;
union sigval sv;
struct pcb *pcb;
switch (type) {
case T_TLB_MOD:
/* check for kernel address */
if (trapframe->badvaddr < 0) {
if (pmap_emulate_modify(pmap_kernel(),
trapframe->badvaddr)) {
/* write to read only page in the kernel */
ftype = PROT_WRITE;
pcb = &p->p_addr->u_pcb;
goto kernel_fault;
}
return;
}
/* FALLTHROUGH */
case T_TLB_MOD+T_USER:
if (pmap_emulate_modify(p->p_vmspace->vm_map.pmap,
trapframe->badvaddr)) {
/* write to read only page */
ftype = PROT_WRITE;
pcb = &p->p_addr->u_pcb;
goto fault_common_no_miss;
}
return;
case T_TLB_LD_MISS:
case T_TLB_ST_MISS:
ftype = (type == T_TLB_ST_MISS) ? PROT_WRITE : PROT_READ;
pcb = &p->p_addr->u_pcb;
/* check for kernel address */
if (trapframe->badvaddr < 0) {
vaddr_t va;
int rv;
kernel_fault:
va = trunc_page((vaddr_t)trapframe->badvaddr);
onfault = pcb->pcb_onfault;
pcb->pcb_onfault = 0;
KERNEL_LOCK();
rv = uvm_fault(kernel_map, va, 0, ftype);
KERNEL_UNLOCK();
pcb->pcb_onfault = onfault;
if (rv == 0)
return;
if (onfault != 0) {
pcb->pcb_onfault = 0;
trapframe->pc = onfault_table[onfault];
return;
}
goto err;
}
/*
* It is an error for the kernel to access user space except
* through the copyin/copyout routines.
*/
if (pcb->pcb_onfault != 0) {
/*
* We want to resolve the TLB fault before invoking
* pcb_onfault if necessary.
*/
goto fault_common;
} else {
goto err;
}
case T_TLB_LD_MISS+T_USER:
ftype = PROT_READ;
pcb = &p->p_addr->u_pcb;
goto fault_common;
case T_TLB_ST_MISS+T_USER:
ftype = PROT_WRITE;
pcb = &p->p_addr->u_pcb;
fault_common:
#ifdef CPU_R4000
if (r4000_errata != 0) {
if (eop_tlb_miss_handler(trapframe, ci, p) != 0)
return;
}
#endif
fault_common_no_miss:
#ifdef CPU_R4000
if (r4000_errata != 0) {
eop_cleanup(trapframe, p);
}
#endif
{
vaddr_t va;
struct vmspace *vm;
vm_map_t map;
int rv;
vm = p->p_vmspace;
map = &vm->vm_map;
va = trunc_page((vaddr_t)trapframe->badvaddr);
onfault = pcb->pcb_onfault;
pcb->pcb_onfault = 0;
KERNEL_LOCK();
rv = uvm_fault(map, va, 0, ftype);
pcb->pcb_onfault = onfault;
/*
* If this was a stack access we keep track of the maximum
* accessed stack size. Also, if vm_fault gets a protection
* failure it is due to accessing the stack region outside
* the current limit and we need to reflect that as an access
* error.
*/
if ((caddr_t)va >= vm->vm_maxsaddr) {
if (rv == 0)
uvm_grow(p, va);
else if (rv == EACCES)
rv = EFAULT;
}
KERNEL_UNLOCK();
if (rv == 0)
return;
if (!USERMODE(trapframe->sr)) {
if (onfault != 0) {
pcb->pcb_onfault = 0;
trapframe->pc = onfault_table[onfault];
return;
}
goto err;
}
ucode = ftype;
i = SIGSEGV;
typ = SEGV_MAPERR;
break;
}
case T_ADDR_ERR_LD+T_USER: /* misaligned or kseg access */
case T_ADDR_ERR_ST+T_USER: /* misaligned or kseg access */
ucode = 0; /* XXX should be PROT_something */
i = SIGBUS;
typ = BUS_ADRALN;
break;
case T_BUS_ERR_IFETCH+T_USER: /* BERR asserted to cpu */
case T_BUS_ERR_LD_ST+T_USER: /* BERR asserted to cpu */
ucode = 0; /* XXX should be PROT_something */
i = SIGBUS;
typ = BUS_OBJERR;
break;
case T_SYSCALL+T_USER:
{
struct trapframe *locr0 = p->p_md.md_regs;
struct sysent *callp;
unsigned int code;
register_t tpc;
int numsys, error;
struct args {
register_t i[8];
} args;
register_t rval[2];
atomic_inc_int(&uvmexp.syscalls);
/* compute next PC after syscall instruction */
tpc = trapframe->pc; /* Remember if restart */
if (trapframe->cause & CR_BR_DELAY)
locr0->pc = MipsEmulateBranch(locr0,
trapframe->pc, 0, 0);
else
locr0->pc += 4;
callp = p->p_p->ps_emul->e_sysent;
numsys = p->p_p->ps_emul->e_nsysent;
code = locr0->v0;
switch (code) {
case SYS_syscall:
case SYS___syscall:
/*
* Code is first argument, followed by actual args.
* __syscall provides the code as a quad to maintain
* proper alignment of 64-bit arguments on 32-bit
* platforms, which doesn't change anything here.
*/
code = locr0->a0;
if (code >= numsys)
callp += p->p_p->ps_emul->e_nosys; /* (illegal) */
else
callp += code;
i = callp->sy_argsize / sizeof(register_t);
args.i[0] = locr0->a1;
args.i[1] = locr0->a2;
args.i[2] = locr0->a3;
if (i > 3) {
args.i[3] = locr0->a4;
args.i[4] = locr0->a5;
args.i[5] = locr0->a6;
args.i[6] = locr0->a7;
if (i > 7)
if ((error = copyin((void *)locr0->sp,
&args.i[7], sizeof(register_t))))
goto bad;
}
break;
default:
if (code >= numsys)
callp += p->p_p->ps_emul->e_nosys; /* (illegal) */
else
callp += code;
i = callp->sy_narg;
args.i[0] = locr0->a0;
args.i[1] = locr0->a1;
args.i[2] = locr0->a2;
args.i[3] = locr0->a3;
if (i > 4) {
args.i[4] = locr0->a4;
args.i[5] = locr0->a5;
args.i[6] = locr0->a6;
args.i[7] = locr0->a7;
}
}
rval[0] = 0;
rval[1] = locr0->v1;
#if defined(DDB) || defined(DEBUG)
trapdebug[TRAPSIZE * ci->ci_cpuid + (trppos[ci->ci_cpuid] == 0 ?
TRAPSIZE : trppos[ci->ci_cpuid]) - 1].code = code;
#endif
error = mi_syscall(p, code, callp, args.i, rval);
switch (error) {
case 0:
locr0->v0 = rval[0];
locr0->v1 = rval[1];
locr0->a3 = 0;
break;
case ERESTART:
locr0->pc = tpc;
break;
case EJUSTRETURN:
break; /* nothing to do */
default:
bad:
locr0->v0 = error;
locr0->a3 = 1;
}
mi_syscall_return(p, code, error, rval);
return;
}
case T_BREAK:
#ifdef DDB
db_ktrap(type, trapframe);
#endif
/* Reenable interrupts if necessary */
if (trapframe->sr & SR_INT_ENAB) {
enableintr();
}
return;
case T_BREAK+T_USER:
{
caddr_t va;
u_int32_t instr;
struct trapframe *locr0 = p->p_md.md_regs;
/* compute address of break instruction */
va = (caddr_t)trapframe->pc;
if (trapframe->cause & CR_BR_DELAY)
va += 4;
/* read break instruction */
copyin(va, &instr, sizeof(int32_t));
switch ((instr & BREAK_VAL_MASK) >> BREAK_VAL_SHIFT) {
case 6: /* gcc range error */
i = SIGFPE;
typ = FPE_FLTSUB;
/* skip instruction */
if (trapframe->cause & CR_BR_DELAY)
locr0->pc = MipsEmulateBranch(locr0,
trapframe->pc, 0, 0);
else
locr0->pc += 4;
break;
case 7: /* gcc3 divide by zero */
i = SIGFPE;
typ = FPE_INTDIV;
/* skip instruction */
if (trapframe->cause & CR_BR_DELAY)
locr0->pc = MipsEmulateBranch(locr0,
trapframe->pc, 0, 0);
else
locr0->pc += 4;
break;
#ifdef PTRACE
case BREAK_SSTEP_VAL:
if (p->p_md.md_ss_addr == (long)va) {
#ifdef DEBUG
printf("trap: %s (%d): breakpoint at %p "
"(insn %08x)\n",
p->p_comm, p->p_pid,
(void *)p->p_md.md_ss_addr,
p->p_md.md_ss_instr);
#endif
/* Restore original instruction and clear BP */
KERNEL_LOCK();
process_sstep(p, 0);
KERNEL_UNLOCK();
typ = TRAP_BRKPT;
} else {
typ = TRAP_TRACE;
}
i = SIGTRAP;
break;
#endif
#ifdef FPUEMUL
case BREAK_FPUEMUL_VAL:
/*
* If this is a genuine FP emulation break,
* resume execution to our branch destination.
*/
if ((p->p_md.md_flags & MDP_FPUSED) != 0 &&
p->p_md.md_fppgva + 4 == (vaddr_t)va) {
struct vm_map *map = &p->p_vmspace->vm_map;
p->p_md.md_flags &= ~MDP_FPUSED;
locr0->pc = p->p_md.md_fpbranchva;
/*
* Prevent access to the relocation page.
* XXX needs to be fixed to work with rthreads
*/
KERNEL_LOCK();
uvm_fault_unwire(map, p->p_md.md_fppgva,
p->p_md.md_fppgva + PAGE_SIZE);
KERNEL_UNLOCK();
(void)uvm_map_protect(map, p->p_md.md_fppgva,
p->p_md.md_fppgva + PAGE_SIZE,
PROT_NONE, FALSE);
return;
}
/* FALLTHROUGH */
#endif
default:
typ = TRAP_TRACE;
i = SIGTRAP;
break;
}
break;
}
case T_IWATCH+T_USER:
case T_DWATCH+T_USER:
{
caddr_t va;
/* compute address of trapped instruction */
va = (caddr_t)trapframe->pc;
if (trapframe->cause & CR_BR_DELAY)
va += 4;
printf("watch exception @ %p\n", va);
#ifdef RM7K_PERFCNTR
if (rm7k_watchintr(trapframe)) {
/* Return to user, don't add any more overhead */
return;
}
#endif
i = SIGTRAP;
typ = TRAP_BRKPT;
break;
}
case T_TRAP+T_USER:
{
caddr_t va;
u_int32_t instr;
struct trapframe *locr0 = p->p_md.md_regs;
/* compute address of trap instruction */
va = (caddr_t)trapframe->pc;
if (trapframe->cause & CR_BR_DELAY)
va += 4;
/* read break instruction */
copyin(va, &instr, sizeof(int32_t));
if (trapframe->cause & CR_BR_DELAY)
locr0->pc = MipsEmulateBranch(locr0,
trapframe->pc, 0, 0);
else
locr0->pc += 4;
#ifdef RM7K_PERFCNTR
if (instr == 0x040c0000) { /* Performance cntr trap */
int result;
result = rm7k_perfcntr(trapframe->a0, trapframe->a1,
trapframe->a2, trapframe->a3);
locr0->v0 = -result;
/* Return to user, don't add any more overhead */
return;
} else
#endif
/*
* GCC 4 uses teq with code 7 to signal divide by
* zero at runtime. This is one instruction shorter
* than the BEQ + BREAK combination used by gcc 3.
*/
if ((instr & 0xfc00003f) == 0x00000034 /* teq */ &&
(instr & 0x001fffc0) == ((ZERO << 16) | (7 << 6))) {
i = SIGFPE;
typ = FPE_INTDIV;
} else {
i = SIGEMT; /* Stuff it with something for now */
typ = 0;
}
break;
}
case T_RES_INST+T_USER:
i = SIGILL;
typ = ILL_ILLOPC;
break;
case T_COP_UNUSABLE+T_USER:
/*
* Note MIPS IV COP1X instructions issued with FPU
* disabled correctly report coprocessor 1 as the
* unusable coprocessor number.
*/
if ((trapframe->cause & CR_COP_ERR) != CR_COP1_ERR) {
i = SIGILL; /* only FPU instructions allowed */
typ = ILL_ILLOPC;
break;
}
#ifdef FPUEMUL
MipsFPTrap(trapframe);
#else
enable_fpu(p);
#endif
return;
case T_FPE:
printf("FPU Trap: PC %lx CR %lx SR %lx\n",
trapframe->pc, trapframe->cause, trapframe->sr);
goto err;
case T_FPE+T_USER:
MipsFPTrap(trapframe);
return;
case T_OVFLOW+T_USER:
i = SIGFPE;
typ = FPE_FLTOVF;
break;
case T_ADDR_ERR_LD: /* misaligned access */
case T_ADDR_ERR_ST: /* misaligned access */
case T_BUS_ERR_LD_ST: /* BERR asserted to cpu */
pcb = &p->p_addr->u_pcb;
if ((onfault = pcb->pcb_onfault) != 0) {
pcb->pcb_onfault = 0;
trapframe->pc = onfault_table[onfault];
return;
}
goto err;
#ifdef CPU_R10000
case T_BUS_ERR_IFETCH:
/*
* At least R16000 processor have been found triggering
* reproduceable bus error on instruction fetch in the
* kernel code, which are trivially recoverable (and
* look like an obscure errata to me).
*
* Thus, ignore these exceptions if the faulting address
* is in the kernel.
*/
{
extern void *kernel_text;
extern void *etext;
vaddr_t va;
va = (vaddr_t)trapframe->pc;
if (trapframe->cause & CR_BR_DELAY)
va += 4;
if (va > (vaddr_t)&kernel_text && va < (vaddr_t)&etext)
return;
}
goto err;
#endif
default:
err:
disableintr();
#if !defined(DDB) && defined(DEBUG)
trapDump("trap", printf);
#endif
printf("\nTrap cause = %d Frame %p\n", type, trapframe);
printf("Trap PC %p RA %p fault %p\n",
(void *)trapframe->pc, (void *)trapframe->ra,
(void *)trapframe->badvaddr);
#ifdef DDB
stacktrace(!USERMODE(trapframe->sr) ? trapframe : p->p_md.md_regs);
db_ktrap(type, trapframe);
#endif
panic("trap");
}
#ifdef FPUEMUL
/*
* If a relocated delay slot causes an exception, blame the
* original delay slot address - userland is not supposed to
* know anything about emulation bowels.
*/
if ((p->p_md.md_flags & MDP_FPUSED) != 0 &&
trapframe->badvaddr == p->p_md.md_fppgva)
trapframe->badvaddr = p->p_md.md_fpslotva;
#endif
p->p_md.md_regs->pc = trapframe->pc;
p->p_md.md_regs->cause = trapframe->cause;
p->p_md.md_regs->badvaddr = trapframe->badvaddr;
sv.sival_ptr = (void *)trapframe->badvaddr;
KERNEL_LOCK();
trapsignal(p, i, ucode, typ, sv);
KERNEL_UNLOCK();
}
/*
* Handle an exception.
* In the case of a kernel trap, we return the pc where to resume if
* pcb_onfault is set, otherwise, return old pc.
*/
void
trap(struct trapframe *trapframe)
{
struct cpu_info *ci = curcpu();
struct proc *p = ci->ci_curproc;
int type;
type = (trapframe->cause & CR_EXC_CODE) >> CR_EXC_CODE_SHIFT;
#if defined(CPU_R8000) && !defined(DEBUG_INTERRUPT)
if (type != T_INT)
#endif
trapdebug_enter(ci, trapframe, -1);
#ifdef CPU_R8000
if (type != T_INT && type != T_SYSCALL)
#else
if (type != T_SYSCALL)
#endif
atomic_inc_int(&uvmexp.traps);
if (USERMODE(trapframe->sr))
type |= T_USER;
/*
* Enable hardware interrupts if they were on before the trap;
* enable IPI interrupts only otherwise.
*/
switch (type) {
#ifdef CPU_R8000
case T_INT:
case T_INT | T_USER:
#endif
case T_BREAK:
break;
default:
if (ISSET(trapframe->sr, SR_INT_ENAB))
enableintr();
else {
#ifdef MULTIPROCESSOR
ENABLEIPI();
#endif
}
break;
}
#ifdef CPU_R8000
/*
* Some exception causes on R8000 are actually detected by external
* circuitry, and as such are reported as external interrupts.
* On R8000 kernels, external interrupts vector to trap() instead of
* interrupt(), so that we can process these particular exceptions
* as if they were triggered as regular exceptions.
*/
if ((type & ~T_USER) == T_INT) {
if (trapframe->cause & CR_VCE) {
#ifndef DEBUG_INTERRUPT
trapdebug_enter(ci, trapframe, -1);
#endif
panic("VCE or TLBX");
}
if (trapframe->cause & CR_FPE) {
#ifndef DEBUG_INTERRUPT
trapdebug_enter(ci, trapframe, -1);
#endif
atomic_inc_int(&uvmexp.traps);
if (type & T_USER)
refreshcreds(p);
itsa(trapframe, ci, p, T_FPE | (type & T_USER));
cp0_reset_cause(CR_FPE);
}
if (trapframe->cause & CR_INT_MASK) {
/*
* Similar reality check as done in interrupt(), in
* case an interrupt occured between a write to
* COP_0_STATUS_REG and it taking effect.
* (I have never seen this occuring on R8000 but
* this is cheap)
*/
if (ISSET(trapframe->sr, SR_INT_ENAB))
interrupt(trapframe);
}
if ((trapframe->cause & CR_FPE) && (type & T_USER))
userret(p);
return;
}
#endif
if (type & T_USER)
refreshcreds(p);
itsa(trapframe, ci, p, type);
if (type & T_USER)
userret(p);
}
