/***************************************************************************//** * @brief axiadc_set_pnsel *******************************************************************************/ int axiadc_set_pnsel(struct axiadc_state *st, int channel, enum adc_pn_sel sel) { unsigned reg; uint32_t version = axiadc_read(st, 0x4000); if (PCORE_VERSION_MAJOR(version) > 7) { reg = axiadc_read(st, ADI_REG_CHAN_CNTRL_3(channel)); reg &= ~ADI_ADC_PN_SEL(~0); reg |= ADI_ADC_PN_SEL(sel); axiadc_write(st, ADI_REG_CHAN_CNTRL_3(channel), reg); } else { reg = axiadc_read(st, ADI_REG_CHAN_CNTRL(channel)); if (sel == ADC_PN_CUSTOM) { reg |= ADI_PN_SEL; } else if (sel == ADC_PN9) { reg &= ~ADI_PN23_TYPE; reg &= ~ADI_PN_SEL; } else { reg |= ADI_PN23_TYPE; reg &= ~ADI_PN_SEL; } axiadc_write(st, ADI_REG_CHAN_CNTRL(channel), reg); } return 0; }
enum adc_pn_sel axiadc_get_pnsel(struct axiadc_state *st, int channel, const char **name) { unsigned val; if (PCORE_VERSION_MAJOR(st->pcore_version) > 7) { const char *ident[] = {"PN9", "PN23A", "UNDEF", "UNDEF", "PN7", "PN15", "PN23", "PN31", "UNDEF", "PN_CUSTOM"}; val = ADI_TO_ADC_PN_SEL(axiadc_read(st, ADI_REG_CHAN_CNTRL_3(channel))); if (name) *name = ident[val]; return val; } else { val = axiadc_read(st, ADI_REG_CHAN_CNTRL(channel));; if (name) { if (val & ADI_PN_SEL) *name = "PN_CUSTOM"; else if (val & ADI_PN23_TYPE) *name = "PN23"; else *name = "PN9"; } return val & (ADI_PN23_TYPE | ADI_PN_SEL); } }
/** * Digital interface timing analysis. * @param phy The AD9361 state structure. * @param buf The buffer. * @param buflen The buffer length. * @return The size in case of success, negative error code otherwise. */ int32_t ad9361_dig_interface_timing_analysis(struct ad9361_rf_phy *phy, char *buf, int32_t buflen) { struct axiadc_state *st = phy->adc_state; int32_t ret, i, j, chan, len = 0; uint8_t field[16][16]; uint8_t rx; dev_dbg(&phy->spi->dev, "%s:\n", __func__); rx = ad9361_spi_read(phy->spi, REG_RX_CLOCK_DATA_DELAY); ad9361_bist_prbs(phy, BIST_INJ_RX); for (i = 0; i < 16; i++) { for (j = 0; j < 16; j++) { ad9361_spi_write(phy->spi, REG_RX_CLOCK_DATA_DELAY, DATA_CLK_DELAY(j) | RX_DATA_DELAY(i)); for (chan = 0; chan < 4; chan++) axiadc_write(st, ADI_REG_CHAN_STATUS(chan), ADI_PN_ERR | ADI_PN_OOS); mdelay(1); if (axiadc_read(st, ADI_REG_STATUS) & ADI_STATUS) { for (chan = 0, ret = 0; chan < 4; chan++) ret |= axiadc_read(st, ADI_REG_CHAN_STATUS(chan)); } else { ret = 1; } field[i][j] = ret; } } ad9361_spi_write(phy->spi, REG_RX_CLOCK_DATA_DELAY, rx); ad9361_bist_prbs(phy, BIST_DISABLE); len += snprintf(buf + len, buflen, "CLK: %"PRIu32" Hz 'o' = PASS\n", clk_get_rate(phy, phy->ref_clk_scale[RX_SAMPL_CLK])); len += snprintf(buf + len, buflen, "DC"); for (i = 0; i < 16; i++) len += snprintf(buf + len, buflen, "%"PRIx32":", i); len += snprintf(buf + len, buflen, "\n"); for (i = 0; i < 16; i++) { len += snprintf(buf + len, buflen, "%"PRIx32":", i); for (j = 0; j < 16; j++) { len += snprintf(buf + len, buflen, "%c ", (field[i][j] ? '.' : 'o')); } len += snprintf(buf + len, buflen, "\n"); } len += snprintf(buf + len, buflen, "\n"); return len; }
static int axiadc_reg_access(struct iio_dev *indio_dev, unsigned reg, unsigned writeval, unsigned *readval) { struct axiadc_state *st = iio_priv(indio_dev); int ret; mutex_lock(&indio_dev->mlock); if (readval == NULL) { if (reg & DEBUGFS_DRA_PCORE_REG_MAGIC) { axiadc_write(st, reg & 0xFFFF, writeval); ret = 0; } else { ret = axiadc_spi_write(st, reg, writeval); axiadc_spi_write(st, ADC_REG_TRANSFER, TRANSFER_SYNC); } } else { if (reg & DEBUGFS_DRA_PCORE_REG_MAGIC) { *readval = axiadc_read(st, reg & 0xFFFF); } else { ret = axiadc_spi_read(st, reg); if (ret < 0) goto out_unlock; *readval = ret; } ret = 0; } out_unlock: mutex_unlock(&indio_dev->mlock); return ret; }
static ssize_t axiadc_debugfs_pncheck_read(struct file *file, char __user *userbuf, size_t count, loff_t *ppos) { struct iio_dev *indio_dev = file->private_data; struct axiadc_state *st = iio_priv(indio_dev); struct axiadc_converter *conv = to_converter(st->dev_spi); char buf[1000]; const char *pn_name; ssize_t len = 0; unsigned stat, i; for (i = 0; i < conv->chip_info->num_channels; i++) { stat = axiadc_read(st, ADI_REG_CHAN_STATUS(i)); axiadc_get_pnsel(st, i, &pn_name); len += sprintf(buf + len, "CH%d : %s : %s %s\n", i, pn_name, (stat & ADI_PN_OOS) ? "Out of Sync :" : "In Sync :", (stat & (ADI_PN_ERR | ADI_PN_OOS)) ? "PN Error" : "OK"); axiadc_write(st, ADI_REG_CHAN_STATUS(i), ~0); if (len > 955) return -ENOMEM; } return simple_read_from_buffer(userbuf, count, ppos, buf, len); }
/** * HDL loopback enable/disable. * @param phy The AD9361 state structure. * @param enable Enable/disable option. * @return 0 in case of success, negative error code otherwise. */ int32_t ad9361_hdl_loopback(struct ad9361_rf_phy *phy, bool enable) { struct axiadc_converter *conv = phy->adc_conv; struct axiadc_state *st = phy->adc_state; int32_t reg, addr, chan; uint32_t version = axiadc_read(st, 0x4000); /* Still there but implemented a bit different */ if (PCORE_VERSION_MAJOR(version) > 7) addr = 0x4418; else addr = 0x4414; for (chan = 0; chan < conv->chip_info->num_channels; chan++) { reg = axiadc_read(st, addr + (chan) * 0x40); if (PCORE_VERSION_MAJOR(version) > 7) { if (enable && reg != 0x8) { conv->scratch_reg[chan] = reg; reg = 0x8; } else if (reg == 0x8) { reg = conv->scratch_reg[chan]; } } else { /* DAC_LB_ENB If set enables loopback of receive data */ if (enable) reg |= BIT(1); else reg &= ~BIT(1); } axiadc_write(st, addr + (chan) * 0x40, reg); } return 0; }
/** * Digital tune IO delay. * @param phy The AD9361 state structure. * @param tx The Synthesizer TX = 1, RX = 0. * @return 0 in case of success, negative error code otherwise. */ static int32_t ad9361_dig_tune_iodelay(struct ad9361_rf_phy *phy, bool tx) { struct axiadc_converter *conv = phy->adc_conv; struct axiadc_state *st = phy->adc_state; int32_t ret, i, j, chan, num_chan; uint32_t s0, c0; uint8_t field[32]; num_chan = (conv->chip_info->num_channels > 4) ? 4 : conv->chip_info->num_channels; for (i = 0; i < 7; i++) { for (j = 0; j < 32; j++) { ad9361_iodelay_set(st, i, j, tx); mdelay(1); for (chan = 0; chan < num_chan; chan++) axiadc_write(st, ADI_REG_CHAN_STATUS(chan), ADI_PN_ERR | ADI_PN_OOS); mdelay(10); for (chan = 0, ret = 0; chan < num_chan; chan++) ret |= axiadc_read(st, ADI_REG_CHAN_STATUS(chan)); field[j] = ret; } c0 = ad9361_find_opt(&field[0], 32, &s0); ad9361_iodelay_set(st, i, s0 + c0 / 2, tx); dev_dbg(&phy->spi->dev, "%s Lane %"PRId32", window cnt %"PRIu32" , start %"PRIu32", IODELAY set to %"PRIu32"\n", tx ? "TX" :"RX", i , c0, s0, s0 + c0 / 2); } return 0; }
/** * Setup the AD9361 device. * @param phy The AD9361 state structure. * @return 0 in case of success, negative error code otherwise. */ int32_t ad9361_post_setup(struct ad9361_rf_phy *phy) { struct axiadc_converter *conv = phy->adc_conv; struct axiadc_state *st = phy->adc_state; int32_t rx2tx2 = phy->pdata->rx2tx2; int32_t tmp, num_chan, flags; int32_t i, ret; num_chan = (conv->chip_info->num_channels > 4) ? 4 : conv->chip_info->num_channels; axiadc_write(st, ADI_REG_CNTRL, rx2tx2 ? 0 : ADI_R1_MODE); tmp = axiadc_read(st, 0x4048); if (!rx2tx2) { axiadc_write(st, 0x4048, tmp | BIT(5)); /* R1_MODE */ axiadc_write(st, 0x404c, (phy->pdata->port_ctrl.pp_conf[2] & LVDS_MODE) ? 1 : 0); /* RATE */ } else { tmp &= ~BIT(5); axiadc_write(st, 0x4048, tmp); axiadc_write(st, 0x404c, (phy->pdata->port_ctrl.pp_conf[2] & LVDS_MODE) ? 3 : 1); /* RATE */ } #ifdef ALTERA_PLATFORM axiadc_write(st, 0x404c, 1); #endif for (i = 0; i < num_chan; i++) { axiadc_write(st, ADI_REG_CHAN_CNTRL_1(i), ADI_DCFILT_OFFSET(0)); axiadc_write(st, ADI_REG_CHAN_CNTRL_2(i), (i & 1) ? 0x00004000 : 0x40000000); axiadc_write(st, ADI_REG_CHAN_CNTRL(i), ADI_FORMAT_SIGNEXT | ADI_FORMAT_ENABLE | ADI_ENABLE | ADI_IQCOR_ENB); } flags = 0x0; ret = ad9361_dig_tune(phy, ((conv->chip_info->num_channels > 4) || axiadc_read(st, 0x0004)) ? 0 : 61440000, flags); if (ret < 0) return ret; if (flags & (DO_IDELAY | DO_ODELAY)) { ret = ad9361_dig_tune(phy, (axiadc_read(st, ADI_REG_ID)) ? 0 : 61440000, flags & BE_VERBOSE); if (ret < 0) return ret; } ret = ad9361_set_trx_clock_chain(phy, phy->pdata->rx_path_clks, phy->pdata->tx_path_clks); ad9361_ensm_force_state(phy, ENSM_STATE_ALERT); ad9361_ensm_restore_prev_state(phy); return ret; }
/** * Digital tune. * @param phy The AD9361 state structure. * @param max_freq Maximum frequency. * @param flags Flags: BE_VERBOSE, BE_MOREVERBOSE, DO_IDELAY, DO_ODELAY. * @return 0 in case of success, negative error code otherwise. */ int32_t ad9361_dig_tune(struct ad9361_rf_phy *phy, uint32_t max_freq, enum dig_tune_flags flags) { struct axiadc_converter *conv = phy->adc_conv; struct axiadc_state *st = phy->adc_state; int32_t ret, i, j, k, chan, t, num_chan, err = 0; uint32_t s0, s1, c0, c1, tmp, saved = 0; uint8_t field[2][16]; uint32_t saved_dsel[4], saved_chan_ctrl6[4], saved_chan_ctrl0[4]; uint32_t rates[3] = {25000000U, 40000000U, 61440000U}; uint32_t hdl_dac_version; dev_dbg(&phy->spi->dev, "%s: freq %"PRIu32" flags 0x%X\n", __func__, max_freq, flags); hdl_dac_version = axiadc_read(st, 0x4000); if ((phy->pdata->dig_interface_tune_skipmode == 2) || (flags & RESTORE_DEFAULT)) { /* skip completely and use defaults */ ad9361_spi_write(phy->spi, REG_RX_CLOCK_DATA_DELAY, phy->pdata->port_ctrl.rx_clk_data_delay); ad9361_spi_write(phy->spi, REG_TX_CLOCK_DATA_DELAY, phy->pdata->port_ctrl.tx_clk_data_delay); return 0; } if (flags & DO_IDELAY) ad9361_midscale_iodelay(phy, 0); if (flags & DO_ODELAY) ad9361_midscale_iodelay(phy, 1); if (!phy->pdata->fdd) { ad9361_set_ensm_mode(phy, true, false); ad9361_ensm_force_state(phy, ENSM_STATE_FDD); } else { ad9361_ensm_force_state(phy, ENSM_STATE_ALERT); ad9361_ensm_restore_prev_state(phy); } num_chan = (conv->chip_info->num_channels > 4) ? 4 : conv->chip_info->num_channels; ad9361_bist_prbs(phy, BIST_INJ_RX); for (t = 0; t < 2; t++) { memset(field, 0, 32); for (k = 0; (uint32_t)k < (max_freq ? ARRAY_SIZE(rates) : 1); k++) { if (max_freq) ad9361_set_trx_clock_chain_freq(phy, ((phy->pdata->port_ctrl.pp_conf[2] & LVDS_MODE) || !phy->pdata->rx2tx2) ? rates[k] : rates[k] / 2); for (i = 0; i < 2; i++) { for (j = 0; j < 16; j++) { ad9361_spi_write(phy->spi, REG_RX_CLOCK_DATA_DELAY + t, RX_DATA_DELAY(i == 0 ? j : 0) | DATA_CLK_DELAY(i ? j : 0)); for (chan = 0; chan < num_chan; chan++) axiadc_write(st, ADI_REG_CHAN_STATUS(chan), ADI_PN_ERR | ADI_PN_OOS); mdelay(4); if ((t == 1) || (axiadc_read(st, ADI_REG_STATUS) & ADI_STATUS)) { for (chan = 0, ret = 0; chan < num_chan; chan++) { ret |= axiadc_read(st, ADI_REG_CHAN_STATUS(chan)); } } else { ret = 1; } field[i][j] |= ret; } } if ((flags & BE_MOREVERBOSE) && max_freq) { ad9361_dig_tune_verbose_print(phy, field, t); } } c0 = ad9361_find_opt(&field[0][0], 16, &s0); c1 = ad9361_find_opt(&field[1][0], 16, &s1); if (!c0 && !c1) { ad9361_dig_tune_verbose_print(phy, field, t); dev_err(&phy->spi->dev, "%s: Tuning %s FAILED!", __func__, t ? "TX" : "RX"); err |= -EIO; } else if (flags & BE_VERBOSE) { ad9361_dig_tune_verbose_print(phy, field, t); } if (c1 > c0) ad9361_spi_write(phy->spi, REG_RX_CLOCK_DATA_DELAY + t, DATA_CLK_DELAY(s1 + c1 / 2) | RX_DATA_DELAY(0)); else ad9361_spi_write(phy->spi, REG_RX_CLOCK_DATA_DELAY + t, DATA_CLK_DELAY(0) | RX_DATA_DELAY(s0 + c0 / 2)); if (t == 0) { if (flags & DO_IDELAY) ad9361_dig_tune_iodelay(phy, 0); /* Now do the loopback and tune the digital out */ ad9361_bist_prbs(phy, BIST_DISABLE); axiadc_write(st, ADI_REG_RSTN, ADI_MMCM_RSTN); axiadc_write(st, ADI_REG_RSTN, ADI_RSTN | ADI_MMCM_RSTN); if (phy->pdata->dig_interface_tune_skipmode == 1) { /* skip TX */ if (!(flags & SKIP_STORE_RESULT)) phy->pdata->port_ctrl.rx_clk_data_delay = ad9361_spi_read(phy->spi, REG_RX_CLOCK_DATA_DELAY); if (!phy->pdata->fdd) { ad9361_set_ensm_mode(phy, phy->pdata->fdd, phy->pdata->ensm_pin_ctrl); ad9361_ensm_restore_prev_state(phy); } return 0; } ad9361_bist_loopback(phy, 1); axiadc_write(st, 0x4000 + ADI_REG_RSTN, ADI_RSTN | ADI_MMCM_RSTN); for (chan = 0; chan < num_chan; chan++) { saved_chan_ctrl0[chan] = axiadc_read(st, ADI_REG_CHAN_CNTRL(chan)); axiadc_write(st, ADI_REG_CHAN_CNTRL(chan), ADI_FORMAT_SIGNEXT | ADI_FORMAT_ENABLE | ADI_ENABLE | ADI_IQCOR_ENB); axiadc_set_pnsel(st, chan, ADC_PN_CUSTOM); saved_chan_ctrl6[chan] = axiadc_read(st, 0x4414 + (chan) * 0x40); if (PCORE_VERSION_MAJOR(hdl_dac_version) > 7) { saved_dsel[chan] = axiadc_read(st, 0x4418 + (chan) * 0x40); axiadc_write(st, 0x4418 + (chan) * 0x40, 9); axiadc_write(st, 0x4044, 0x1); } else axiadc_write(st, 0x4414 + (chan) * 0x40, 1); } if (PCORE_VERSION_MAJOR(hdl_dac_version) < 8) { saved = tmp = axiadc_read(st, 0x4048); tmp &= ~0xF; tmp |= 1; axiadc_write(st, 0x4048, tmp); } } else { if (flags & DO_ODELAY) ad9361_dig_tune_iodelay(phy, 1); ad9361_bist_loopback(phy, 0); if (PCORE_VERSION_MAJOR(hdl_dac_version) < 8) axiadc_write(st, 0x4048, saved); for (chan = 0; chan < num_chan; chan++) { axiadc_write(st, ADI_REG_CHAN_CNTRL(chan), saved_chan_ctrl0[chan]); axiadc_set_pnsel(st, chan, ADC_PN9); if (PCORE_VERSION_MAJOR(hdl_dac_version) > 7) { axiadc_write(st, 0x4418 + (chan) * 0x40, saved_dsel[chan]); axiadc_write(st, 0x4044, 0x1); } axiadc_write(st, 0x4414 + (chan) * 0x40, saved_chan_ctrl6[chan]); } if (err == -EIO) { ad9361_spi_write(phy->spi, REG_RX_CLOCK_DATA_DELAY, phy->pdata->port_ctrl.rx_clk_data_delay); ad9361_spi_write(phy->spi, REG_TX_CLOCK_DATA_DELAY, phy->pdata->port_ctrl.tx_clk_data_delay); if (!max_freq) err = 0; } else if (!(flags & SKIP_STORE_RESULT)) { phy->pdata->port_ctrl.rx_clk_data_delay = ad9361_spi_read(phy->spi, REG_RX_CLOCK_DATA_DELAY); phy->pdata->port_ctrl.tx_clk_data_delay = ad9361_spi_read(phy->spi, REG_TX_CLOCK_DATA_DELAY); } if (!phy->pdata->fdd) { ad9361_set_ensm_mode(phy, phy->pdata->fdd, phy->pdata->ensm_pin_ctrl); ad9361_ensm_restore_prev_state(phy); } axiadc_write(st, ADI_REG_RSTN, ADI_MMCM_RSTN); axiadc_write(st, ADI_REG_RSTN, ADI_RSTN | ADI_MMCM_RSTN); return err; } } return -EINVAL; }
static int axiadc_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long m) { struct axiadc_state *st = iio_priv(indio_dev); struct axiadc_converter *conv = to_converter(st->dev_spi); int ret, sign; unsigned tmp, phase = 0; unsigned long long llval; switch (m) { case IIO_CHAN_INFO_CALIBPHASE: phase = 1; case IIO_CHAN_INFO_CALIBSCALE: tmp = axiadc_read(st, ADI_REG_CHAN_CNTRL_2(chan->channel)); /* format is 1.1.14 (sign, integer and fractional bits) */ if (!((phase + chan->channel) % 2)) { tmp = ADI_TO_IQCOR_COEFF_1(tmp); } else { tmp = ADI_TO_IQCOR_COEFF_2(tmp); } if (tmp & 0x8000) sign = -1; else sign = 1; if (tmp & 0x4000) *val = 1 * sign; else *val = 0; tmp &= ~0xC000; llval = tmp * 1000000ULL + (0x4000 / 2); do_div(llval, 0x4000); if (*val == 0) *val2 = llval * sign; else *val2 = llval; return IIO_VAL_INT_PLUS_MICRO; case IIO_CHAN_INFO_CALIBBIAS: tmp = axiadc_read(st, ADI_REG_CHAN_CNTRL_1(chan->channel)); *val = (short)ADI_TO_DCFILT_OFFSET(tmp); return IIO_VAL_INT; case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY: /* * approx: F_cut = C * Fsample / (2 * pi) */ tmp = axiadc_read(st, ADI_REG_CHAN_CNTRL(chan->channel)); if (!(tmp & ADI_DCFILT_ENB)) { *val = 0; return IIO_VAL_INT; } tmp = axiadc_read(st, ADI_REG_CHAN_CNTRL_1(chan->channel)); llval = ADI_TO_DCFILT_COEFF(tmp) * (unsigned long long)conv->adc_clk; do_div(llval, 102944); /* 2 * pi * 0x4000 */ *val = llval; return IIO_VAL_INT; case IIO_CHAN_INFO_SAMP_FREQ: ret = conv->read_raw(indio_dev, chan, val, val2, m); if (ret < 0 || !*val) { tmp = ADI_TO_CLK_FREQ(axiadc_read(st, ADI_REG_CLK_FREQ)); llval = tmp * 100000000ULL /* FIXME */ * ADI_TO_CLK_RATIO(axiadc_read(st, ADI_REG_CLK_RATIO)); *val = llval >> 16; } if (chan->extend_name) { tmp = axiadc_read(st, ADI_REG_CHAN_USR_CNTRL_2(chan->channel)); llval = ADI_TO_USR_DECIMATION_M(tmp) * conv->adc_clk; do_div(llval, ADI_TO_USR_DECIMATION_N(tmp)); *val = llval; } return IIO_VAL_INT; default: return conv->read_raw(indio_dev, chan, val, val2, m); }