static void intel_dsi_device_ready(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
int pipe = intel_crtc->pipe;
u32 val;
DRM_DEBUG_KMS("\n");
mutex_lock(&dev_priv->dpio_lock);
/* program rcomp for compliance, reduce from 50 ohms to 45 ohms
* needed everytime after power gate */
vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
mutex_unlock(&dev_priv->dpio_lock);
/* bandgap reset is needed after everytime we do power gate */
band_gap_reset(dev_priv);
I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_ENTER);
usleep_range(2500, 3000);
val = I915_READ(MIPI_PORT_CTRL(pipe));
I915_WRITE(MIPI_PORT_CTRL(pipe), val | LP_OUTPUT_HOLD);
usleep_range(1000, 1500);
I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_EXIT);
usleep_range(2500, 3000);
I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY);
usleep_range(2500, 3000);
}
static void intel_dsi_mode_set(struct intel_encoder *intel_encoder)
{
struct drm_encoder *encoder = &intel_encoder->base;
struct drm_device *dev = encoder->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
struct drm_display_mode *adjusted_mode =
&intel_crtc->config.adjusted_mode;
int pipe = intel_crtc->pipe;
unsigned int bpp = intel_crtc->config.pipe_bpp;
u32 val, tmp;
DRM_DEBUG_KMS("pipe %c\n", pipe_name(pipe));
/* XXX: Location of the call */
band_gap_reset(dev_priv);
/* escape clock divider, 20MHz, shared for A and C. device ready must be
* off when doing this! txclkesc? */
tmp = I915_READ(MIPI_CTRL(0));
tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
I915_WRITE(MIPI_CTRL(0), tmp | ESCAPE_CLOCK_DIVIDER_1);
/* read request priority is per pipe */
tmp = I915_READ(MIPI_CTRL(pipe));
tmp &= ~READ_REQUEST_PRIORITY_MASK;
I915_WRITE(MIPI_CTRL(pipe), tmp | READ_REQUEST_PRIORITY_HIGH);
/* XXX: why here, why like this? handling in irq handler?! */
I915_WRITE(MIPI_INTR_STAT(pipe), 0xffffffff);
I915_WRITE(MIPI_INTR_EN(pipe), 0xffffffff);
I915_WRITE(MIPI_DPHY_PARAM(pipe), intel_dsi->dphy_reg);
I915_WRITE(MIPI_DPI_RESOLUTION(pipe),
adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT |
adjusted_mode->hdisplay << HORIZONTAL_ADDRESS_SHIFT);
set_dsi_timings(encoder, adjusted_mode);
val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
if (is_cmd_mode(intel_dsi)) {
val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
} else {
val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
/* XXX: cross-check bpp vs. pixel format? */
val |= intel_dsi->pixel_format;
}
I915_WRITE(MIPI_DSI_FUNC_PRG(pipe), val);
/* timeouts for recovery. one frame IIUC. if counter expires, EOT and
* stop state. */
/*
* In burst mode, value greater than one DPI line Time in byte clock
* (txbyteclkhs) To timeout this timer 1+ of the above said value is
* recommended.
*
* In non-burst mode, Value greater than one DPI frame time in byte
* clock(txbyteclkhs) To timeout this timer 1+ of the above said value
* is recommended.
*
* In DBI only mode, value greater than one DBI frame time in byte
* clock(txbyteclkhs) To timeout this timer 1+ of the above said value
* is recommended.
*/
if (is_vid_mode(intel_dsi) &&
intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe),
txbyteclkhs(adjusted_mode->htotal, bpp,
intel_dsi->lane_count) + 1);
} else {
I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe),
txbyteclkhs(adjusted_mode->vtotal *
adjusted_mode->htotal,
bpp, intel_dsi->lane_count) + 1);
}
I915_WRITE(MIPI_LP_RX_TIMEOUT(pipe), intel_dsi->lp_rx_timeout);
I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(pipe), intel_dsi->turn_arnd_val);
I915_WRITE(MIPI_DEVICE_RESET_TIMER(pipe), intel_dsi->rst_timer_val);
/* dphy stuff */
/* in terms of low power clock */
I915_WRITE(MIPI_INIT_COUNT(pipe), txclkesc(ESCAPE_CLOCK_DIVIDER_1, 100));
/* recovery disables */
I915_WRITE(MIPI_EOT_DISABLE(pipe), intel_dsi->eot_disable);
/* in terms of txbyteclkhs. actual high to low switch +
* MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
*
* XXX: write MIPI_STOP_STATE_STALL?
*/
I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(pipe),
intel_dsi->hs_to_lp_count);
/* XXX: low power clock equivalence in terms of byte clock. the number
* of byte clocks occupied in one low power clock. based on txbyteclkhs
* and txclkesc. txclkesc time / txbyteclk time * (105 +
* MIPI_STOP_STATE_STALL) / 105.???
*/
I915_WRITE(MIPI_LP_BYTECLK(pipe), intel_dsi->lp_byte_clk);
/* the bw essential for transmitting 16 long packets containing 252
* bytes meant for dcs write memory command is programmed in this
* register in terms of byte clocks. based on dsi transfer rate and the
* number of lanes configured the time taken to transmit 16 long packets
* in a dsi stream varies. */
I915_WRITE(MIPI_DBI_BW_CTRL(pipe), intel_dsi->bw_timer);
I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(pipe),
intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT |
intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
if (is_vid_mode(intel_dsi))
I915_WRITE(MIPI_VIDEO_MODE_FORMAT(pipe),
intel_dsi->video_frmt_cfg_bits |
intel_dsi->video_mode_format);
}
void intel_dsi_device_ready(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
int pipe = intel_crtc->pipe;
u32 tmp;
DRM_DEBUG_KMS("\n");
/* program rcomp for compliance
* reduce form 50 ohms to 45 ohms */
intel_flisdsi_write32(dev_priv, 0x04, 0x00f0);
band_gap_reset(dev_priv);
#ifdef CONFIG_CRYSTAL_COVE
/* Panel Enable */
if (BYT_CR_CONFIG) {
/* cabc disable */
vlv_gpio_nc_write(dev_priv, GPIO_NC_9_PCONF0, 0x2000CC00);
vlv_gpio_nc_write(dev_priv, GPIO_NC_9_PAD, 0x00000004);
/* panel enable */
vlv_gpio_nc_write(dev_priv, GPIO_NC_11_PCONF0, 0x2000CC00);
vlv_gpio_nc_write(dev_priv, GPIO_NC_11_PAD, 0x00000005);
udelay(500);
} else
intel_mid_pmic_writeb(PMIC_PANEL_EN, 0x01);
#else
/* need to code for BYT-CR for example where things have changed */
DRM_ERROR("PANEL Enable to supported yet\n");
#endif
msleep(intel_dsi->panel_on_delay);
if (intel_dsi->dev.dev_ops->panel_reset)
intel_dsi->dev.dev_ops->panel_reset(&intel_dsi->dev);
/* Disable DPOunit clock gating, can stall pipe */
tmp = I915_READ(DPLL(pipe));
tmp |= DPLL_RESERVED_BIT;
I915_WRITE(DPLL(pipe), tmp);
tmp = I915_READ(DSPCLK_GATE_D);
tmp |= VSUNIT_CLOCK_GATE_DISABLE;
I915_WRITE(DSPCLK_GATE_D, tmp);
intel_enable_dsi_pll(intel_dsi);
//in dual display config, dsi 0 is not init. so this function may not
//be called with pipe0. set this flag for pipe0 so that pipe b can work
#ifdef BYT_DUAL_MIPI_DSI
if(pipe != 0)
{
I915_WRITE_BITS(MIPI_PORT_CTRL(0), LP_OUTPUT_HOLD,
LP_OUTPUT_HOLD);
usleep_range(1000, 1500);
}
#endif
I915_WRITE_BITS(MIPI_PORT_CTRL(pipe), LP_OUTPUT_HOLD,
LP_OUTPUT_HOLD);
usleep_range(1000, 1500);
I915_WRITE_BITS(MIPI_DEVICE_READY(pipe), DEVICE_READY |
ULPS_STATE_EXIT, DEVICE_READY |
ULPS_STATE_MASK);
usleep_range(2000, 2500);
I915_WRITE_BITS(MIPI_DEVICE_READY(pipe), DEVICE_READY,
DEVICE_READY | ULPS_STATE_MASK);
usleep_range(2000, 2500);
I915_WRITE_BITS(MIPI_DEVICE_READY(pipe), 0x00,
DEVICE_READY | ULPS_STATE_MASK);
usleep_range(2000, 2500);
I915_WRITE_BITS(MIPI_DEVICE_READY(pipe), DEVICE_READY,
DEVICE_READY | ULPS_STATE_MASK);
usleep_range(2000, 2500);
}
void intel_dsi_device_ready(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
int pipe = intel_crtc->pipe;
u32 tmp;
int count = 1;
DRM_DEBUG_KMS("\n");
/* program rcomp for compliance
* reduce form 50 ohms to 45 ohms */
intel_flisdsi_write32(dev_priv, 0x04, 0x0004);
band_gap_reset(dev_priv);
#ifdef CONFIG_CRYSTAL_COVE
if (BYT_CR_CONFIG) {
/* cabc disable */
vlv_gpio_nc_write(dev_priv, GPIO_NC_9_PCONF0, 0x2000CC00);
vlv_gpio_nc_write(dev_priv, GPIO_NC_9_PAD, 0x00000004);
/* panel enable */
vlv_gpio_nc_write(dev_priv, GPIO_NC_11_PCONF0, 0x2000CC00);
vlv_gpio_nc_write(dev_priv, GPIO_NC_11_PAD, 0x00000005);
udelay(500);
} else
intel_mid_pmic_writeb(PMIC_PANEL_EN, 0x01);
#else
/* need to code for BYT-CR for example where things have changed */
DRM_ERROR("PANEL Enable to supported yet\n");
#endif
msleep(intel_dsi->panel_on_delay);
if (intel_dsi->dev.dev_ops->panel_reset)
intel_dsi->dev.dev_ops->panel_reset(&intel_dsi->dev);
/* Disable DPOunit clock gating, can stall pipe */
tmp = I915_READ(DPLL(pipe));
tmp |= DPLL_RESERVED_BIT;
I915_WRITE(DPLL(pipe), tmp);
tmp = I915_READ(DSPCLK_GATE_D);
tmp |= VSUNIT_CLOCK_GATE_DISABLE;
I915_WRITE(DSPCLK_GATE_D, tmp);
intel_enable_dsi_pll(intel_dsi);
if (intel_dsi->operation_mode == DSI_VIDEO_MODE) {
I915_WRITE_BITS(MIPI_PORT_CTRL(pipe), LP_OUTPUT_HOLD,
LP_OUTPUT_HOLD);
usleep_range(1000, 1500);
if (intel_dsi->dual_link)
count = 2;
do {
I915_WRITE_BITS(MIPI_DEVICE_READY(pipe), DEVICE_READY |
ULPS_STATE_EXIT, DEVICE_READY |
ULPS_STATE_MASK);
usleep_range(2000, 2500);
I915_WRITE_BITS(MIPI_DEVICE_READY(pipe), DEVICE_READY,
DEVICE_READY | ULPS_STATE_MASK);
usleep_range(2000, 2500);
I915_WRITE_BITS(MIPI_DEVICE_READY(pipe), 0x00,
DEVICE_READY | ULPS_STATE_MASK);
usleep_range(2000, 2500);
I915_WRITE_BITS(MIPI_DEVICE_READY(pipe), DEVICE_READY,
DEVICE_READY | ULPS_STATE_MASK);
usleep_range(2000, 2500);
/* For Port C for dual link */
pipe = PIPE_B;
} while (--count > 0);
}
}
