static int bcma_nexus_probe(device_t dev) { int error; switch (bcm_get_platform()->cid.chip_type) { case BHND_CHIPTYPE_BCMA: case BHND_CHIPTYPE_BCMA_ALT: case BHND_CHIPTYPE_UBUS: break; default: return (ENXIO); } if ((error = bcma_probe(dev)) > 0) return (error); /* Set device description */ bhnd_set_default_bus_desc(dev, &bcm_get_platform()->cid); return (BUS_PROBE_SPECIFIC); }
void platform_start(__register_t a0, __register_t a1, __register_t a2, __register_t a3) { vm_offset_t kernend; uint64_t platform_counter_freq; int error; /* clear the BSS and SBSS segments */ kernend = (vm_offset_t)&end; memset(&edata, 0, kernend - (vm_offset_t)(&edata)); mips_postboot_fixup(); /* Initialize pcpu stuff */ mips_pcpu0_init(); #ifdef CFE /* * Initialize CFE firmware trampolines. This must be done * before any CFE APIs are called, including writing * to the CFE console. * * CFE passes the following values in registers: * a0: firmware handle * a2: firmware entry point * a3: entry point seal */ if (a3 == CFE_EPTSEAL) cfe_init(a0, a2); #endif /* Init BCM platform data */ if ((error = bcm_init_platform_data(&bcm_platform_data))) panic("bcm_init_platform_data() failed: %d", error); platform_counter_freq = bcm_get_cpufreq(bcm_get_platform()); /* CP0 ticks every two cycles */ mips_timer_early_init(platform_counter_freq / 2); cninit(); mips_init(); mips_timer_init_params(platform_counter_freq, 1); }
static int bhnd_nvram_cfe_probe(device_t dev) { struct bcm_platform *bp; /* Fetch platform NVRAM I/O context */ bp = bcm_get_platform(); if (bp->nvram_io == NULL) return (ENXIO); KASSERT(bp->nvram_cls != NULL, ("missing NVRAM class")); /* Set the device description */ device_set_desc(dev, bhnd_nvram_data_class_desc(bp->nvram_cls)); /* Refuse wildcard attachments */ return (BUS_PROBE_NOWILDCARD); }
void platform_reset(void) { struct bcm_platform *bp; bool bcm4785war; printf("bcm::platform_reset()\n"); intr_disable(); #ifdef CFE /* Fall back on CFE if reset requested during platform * data initialization */ if (!bcm_platform_data_avail) { cfe_exit(0, 0); while (1); } #endif bp = bcm_get_platform(); bcm4785war = false; /* Handle BCM4785-specific behavior */ if (bp->cid.chip_id == BHND_CHIPID_BCM4785) { bcm4785war = true; /* Switch to async mode */ bcm_bmips_wr_pllcfg3(BMIPS_BCMCFG_PLLCFG3_SM); } /* Set watchdog (PMU or ChipCommon) */ if (bp->pmu_addr != 0x0) { BCM_PMU_WRITE_4(bp, BHND_PMU_WATCHDOG, 1); } else BCM_CHIPC_WRITE_4(bp, CHIPC_WATCHDOG, 1); /* BCM4785 */ if (bcm4785war) { mips_sync(); __asm __volatile("wait"); } while (1); }
static int bhnd_nvram_cfe_attach(device_t dev) { struct bcm_platform *bp; struct bhnd_nvram_cfe_softc *sc; int error; bp = bcm_get_platform(); KASSERT(bp->nvram_io != NULL, ("missing NVRAM I/O context")); KASSERT(bp->nvram_cls != NULL, ("missing NVRAM class")); sc = device_get_softc(dev); sc->dev = dev; error = bhnd_nvram_store_parse_new(&sc->store, bp->nvram_io, bp->nvram_cls); if (error) return (error); return (error); }