u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value) { unsigned long flags; u32 res; spin_lock_irqsave(&cc->gpio_lock, flags); res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value); spin_unlock_irqrestore(&cc->gpio_lock, flags); return res; }
u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value) { unsigned long flags; u32 res; if (cc->core->id.rev < 20) return 0; spin_lock_irqsave(&cc->gpio_lock, flags); res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLDOWN, mask, value); spin_unlock_irqrestore(&cc->gpio_lock, flags); return res; }
u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value) { return bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value); }
u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value) { return bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value); }
u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value) { return bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value); }
u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value) { return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value); }
void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value) { bcma_cc_write32_masked(cc, BCMA_CC_IRQMASK, mask, value); }