void __init plat_time_init(void) { unsigned long hz = 0; /* */ write_c0_count(0); write_c0_compare(0xffff); switch (bcm47xx_bus_type) { #ifdef CONFIG_BCM47XX_SSB case BCM47XX_BUS_TYPE_SSB: hz = ssb_cpu_clock(&bcm47xx_bus.ssb.mipscore) / 2; break; #endif #ifdef CONFIG_BCM47XX_BCMA case BCM47XX_BUS_TYPE_BCMA: hz = bcma_cpu_clock(&bcm47xx_bus.bcma.bus.drv_mips) / 2; break; #endif } if (!hz) hz = 100000000; /* */ mips_hpt_frequency = hz; }
static void bcma_hcd_4716wa(struct bcma_device *dev) { #ifdef CONFIG_BCMA_DRIVER_MIPS /* Work around for 4716 failures. */ if (dev->bus->chipinfo.id == 0x4716) { u32 tmp; tmp = bcma_cpu_clock(&dev->bus->drv_mips); if (tmp >= 480000000) tmp = 0x1846b; /* set CDR to 0x11(fast) */ else if (tmp == 453000000) tmp = 0x1046b; /* set CDR to 0x10(slow) */ else tmp = 0; /* Change Shim mdio control reg to fix host not acking at * high frequencies */ if (tmp) { bcma_write32(dev, 0x524, 0x1); /* write sel to enable */ udelay(500); bcma_write32(dev, 0x524, tmp); udelay(500); bcma_write32(dev, 0x524, 0x4ab); udelay(500); bcma_read32(dev, 0x528); bcma_write32(dev, 0x528, 0x80000000); } } #endif /* CONFIG_BCMA_DRIVER_MIPS */ }