void bcma_core_set_clockmode(struct bcma_device *core, enum bcma_clkmode clkmode) { u16 i; WARN_ON(core->id.id != BCMA_CORE_CHIPCOMMON && core->id.id != BCMA_CORE_PCIE && core->id.id != BCMA_CORE_80211); switch (clkmode) { case BCMA_CLKMODE_FAST: bcma_set32(core, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT); udelay(64); for (i = 0; i < 1500; i++) { if (bcma_read32(core, BCMA_CLKCTLST) & BCMA_CLKCTLST_HAVEHT) { i = 0; break; } udelay(10); } if (i) pr_err("HT force timeout\n"); break; case BCMA_CLKMODE_DYNAMIC: bcma_set32(core, BCMA_CLKCTLST, ~BCMA_CLKCTLST_FORCEHT); break; } }
void si_pmu_init(struct si_pub *sih) { struct bcma_device *core; /* */ core = ai_findcore(sih, BCMA_CORE_CHIPCOMMON, 0); if (ai_get_pmurev(sih) == 1) bcma_mask32(core, CHIPCREGOFFS(pmucontrol), ~PCTL_NOILP_ON_WAIT); else if (ai_get_pmurev(sih) >= 2) bcma_set32(core, CHIPCREGOFFS(pmucontrol), PCTL_NOILP_ON_WAIT); }
void bcma_core_pll_ctl(struct bcma_device *core, u32 req, u32 status, bool on) { u16 i; WARN_ON(req & ~BCMA_CLKCTLST_EXTRESREQ); WARN_ON(status & ~BCMA_CLKCTLST_EXTRESST); if (on) { bcma_set32(core, BCMA_CLKCTLST, req); for (i = 0; i < 10000; i++) { if ((bcma_read32(core, BCMA_CLKCTLST) & status) == status) { i = 0; break; } udelay(10); } if (i) pr_err("PLL enable timeout\n"); } else { pr_warn("Disabling PLL not supported yet!\n"); } }
void si_pmu_spuravoid_pllupdate(struct si_pub *sih, u8 spuravoid) { u32 tmp = 0; struct bcma_device *core; /* */ core = ai_findcore(sih, BCMA_CORE_CHIPCOMMON, 0); switch (ai_get_chip_id(sih)) { case BCM43224_CHIP_ID: case BCM43225_CHIP_ID: if (spuravoid == 1) { bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr), PMU1_PLL0_PLLCTL0); bcma_write32(core, CHIPCREGOFFS(pllcontrol_data), 0x11500010); bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr), PMU1_PLL0_PLLCTL1); bcma_write32(core, CHIPCREGOFFS(pllcontrol_data), 0x000C0C06); bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr), PMU1_PLL0_PLLCTL2); bcma_write32(core, CHIPCREGOFFS(pllcontrol_data), 0x0F600a08); bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr), PMU1_PLL0_PLLCTL3); bcma_write32(core, CHIPCREGOFFS(pllcontrol_data), 0x00000000); bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr), PMU1_PLL0_PLLCTL4); bcma_write32(core, CHIPCREGOFFS(pllcontrol_data), 0x2001E920); bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr), PMU1_PLL0_PLLCTL5); bcma_write32(core, CHIPCREGOFFS(pllcontrol_data), 0x88888815); } else { bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr), PMU1_PLL0_PLLCTL0); bcma_write32(core, CHIPCREGOFFS(pllcontrol_data), 0x11100010); bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr), PMU1_PLL0_PLLCTL1); bcma_write32(core, CHIPCREGOFFS(pllcontrol_data), 0x000c0c06); bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr), PMU1_PLL0_PLLCTL2); bcma_write32(core, CHIPCREGOFFS(pllcontrol_data), 0x03000a08); bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr), PMU1_PLL0_PLLCTL3); bcma_write32(core, CHIPCREGOFFS(pllcontrol_data), 0x00000000); bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr), PMU1_PLL0_PLLCTL4); bcma_write32(core, CHIPCREGOFFS(pllcontrol_data), 0x200005c0); bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr), PMU1_PLL0_PLLCTL5); bcma_write32(core, CHIPCREGOFFS(pllcontrol_data), 0x88888815); } tmp = 1 << 10; break; default: /* */ return; } bcma_set32(core, CHIPCREGOFFS(pmucontrol), tmp); }