static int __init db1200_detect_board(void) { int bid; /* try the DB1200 first */ bcsr_init(DB1200_BCSR_PHYS_ADDR, DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS); if (BCSR_WHOAMI_DB1200 == BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) { unsigned short t = bcsr_read(BCSR_HEXLEDS); bcsr_write(BCSR_HEXLEDS, ~t); if (bcsr_read(BCSR_HEXLEDS) != t) { bcsr_write(BCSR_HEXLEDS, t); return 0; } } /* okay, try the PB1200 then */ bcsr_init(PB1200_BCSR_PHYS_ADDR, PB1200_BCSR_PHYS_ADDR + PB1200_BCSR_HEXLED_OFS); bid = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)); if ((bid == BCSR_WHOAMI_PB1200_DDR1) || (bid == BCSR_WHOAMI_PB1200_DDR2)) { unsigned short t = bcsr_read(BCSR_HEXLEDS); bcsr_write(BCSR_HEXLEDS, ~t); if (bcsr_read(BCSR_HEXLEDS) != t) { bcsr_write(BCSR_HEXLEDS, t); return 0; } } return 1; /* it's neither */ }
int __init db1300_board_setup(void) { unsigned short whoami; bcsr_init(DB1300_BCSR_PHYS_ADDR, DB1300_BCSR_PHYS_ADDR + DB1300_BCSR_HEXLED_OFS); whoami = bcsr_read(BCSR_WHOAMI); if (BCSR_WHOAMI_BOARD(whoami) != BCSR_WHOAMI_DB1300) return -ENODEV; db1300_gpio_config(); printk(KERN_INFO "NetLogic DBAu1300 Development Platform.\n\t" "BoardID %d CPLD Rev %d DaughtercardID %d\n", BCSR_WHOAMI_BOARD(whoami), BCSR_WHOAMI_CPLD(whoami), BCSR_WHOAMI_DCID(whoami)); /* enable UARTs, YAMON only enables #2 */ alchemy_uart_enable(AU1300_UART0_PHYS_ADDR); alchemy_uart_enable(AU1300_UART1_PHYS_ADDR); alchemy_uart_enable(AU1300_UART3_PHYS_ADDR); return 0; }
void __init board_setup(void) { /* initialize board register space */ bcsr_init(DB1000_BCSR_PHYS_ADDR, DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS); printk(KERN_INFO "AMD Alchemy %s Board\n", board_type_str()); }
int __init db1000_board_setup(void) { /* initialize board register space */ bcsr_init(DB1000_BCSR_PHYS_ADDR, DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS); switch (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) { case BCSR_WHOAMI_DB1000: case BCSR_WHOAMI_DB1500: case BCSR_WHOAMI_DB1100: case BCSR_WHOAMI_PB1500: case BCSR_WHOAMI_PB1500R2: case BCSR_WHOAMI_PB1100: pr_info("AMD Alchemy %s Board\n", get_system_type()); return 0; } return -ENODEV; }
void __init board_setup(void) { unsigned short whoami; db1300_gpio_config(); bcsr_init(DB1300_BCSR_PHYS_ADDR, DB1300_BCSR_PHYS_ADDR + DB1300_BCSR_HEXLED_OFS); whoami = bcsr_read(BCSR_WHOAMI); printk(KERN_INFO "NetLogic DBAu1300 Development Platform.\n\t" "BoardID %d CPLD Rev %d DaughtercardID %d\n", BCSR_WHOAMI_BOARD(whoami), BCSR_WHOAMI_CPLD(whoami), BCSR_WHOAMI_DCID(whoami)); alchemy_uart_enable(AU1300_UART0_PHYS_ADDR); alchemy_uart_enable(AU1300_UART1_PHYS_ADDR); alchemy_uart_enable(AU1300_UART3_PHYS_ADDR); }
void __init board_setup(void) { u32 pin_func; bcsr_init(PB1550_BCSR_PHYS_ADDR, PB1550_BCSR_PHYS_ADDR + PB1550_BCSR_HEXLED_OFS); alchemy_gpio2_enable(); /* * Enable PSC1 SYNC for AC'97. Normaly done in audio driver, * but it is board specific code, so put it here. */ pin_func = au_readl(SYS_PINFUNC); au_sync(); pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1; au_writel(pin_func, SYS_PINFUNC); bcsr_write(BCSR_PCMCIA, 0); /* turn off PCMCIA power */ printk(KERN_INFO "AMD Alchemy Pb1550 Board\n"); }
void __init board_setup(void) { volatile void __iomem *base = (volatile void __iomem *)0xac000000UL; bcsr_init(DB1000_BCSR_PHYS_ADDR, DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS); /* Set AUX clock to 12 MHz * 8 = 96 MHz */ au_writel(8, SYS_AUXPLL); alchemy_gpio1_input_enable(); udelay(100); #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) { u32 pin_func, sys_freqctrl, sys_clksrc; /* Configure pins GPIO[14:9] as GPIO */ pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_UR3; /* Zero and disable FREQ2 */ sys_freqctrl = au_readl(SYS_FREQCTRL0); sys_freqctrl &= ~0xFFF00000; au_writel(sys_freqctrl, SYS_FREQCTRL0); /* Zero and disable USBH/USBD/IrDA clock */ sys_clksrc = au_readl(SYS_CLKSRC); sys_clksrc &= ~(SYS_CS_CIR | SYS_CS_DIR | SYS_CS_MIR_MASK); au_writel(sys_clksrc, SYS_CLKSRC); sys_freqctrl = au_readl(SYS_FREQCTRL0); sys_freqctrl &= ~0xFFF00000; sys_clksrc = au_readl(SYS_CLKSRC); sys_clksrc &= ~(SYS_CS_CIR | SYS_CS_DIR | SYS_CS_MIR_MASK); /* FREQ2 = aux / 2 = 48 MHz */ sys_freqctrl |= (0 << SYS_FC_FRDIV2_BIT) | SYS_FC_FE2 | SYS_FC_FS2; au_writel(sys_freqctrl, SYS_FREQCTRL0); /* * Route 48 MHz FREQ2 into USBH/USBD/IrDA */ sys_clksrc |= SYS_CS_MUX_FQ2 << SYS_CS_MIR_BIT; au_writel(sys_clksrc, SYS_CLKSRC); /* Setup the static bus controller */ au_writel(0x00000002, MEM_STCFG3); /* type = PCMCIA */ au_writel(0x280E3D07, MEM_STTIME3); /* 250ns cycle time */ au_writel(0x10000000, MEM_STADDR3); /* any PCMCIA select */ /* * Get USB Functionality pin state (device vs host drive pins). */ pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_USB; /* 2nd USB port is USB host. */ pin_func |= SYS_PF_USB; au_writel(pin_func, SYS_PINFUNC); } #endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */ /* Enable sys bus clock divider when IDLE state or no bus activity. */ au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL); /* Enable the RTC if not already enabled. */ if (!(readb(base + 0x28) & 0x20)) { writeb(readb(base + 0x28) | 0x20, base + 0x28); au_sync(); } /* Put the clock in BCD mode. */ if (readb(base + 0x2C) & 0x4) { /* reg B */ writeb(readb(base + 0x2c) & ~0x4, base + 0x2c); au_sync(); } }
void __init board_setup(void) { printk(KERN_INFO "AMD Alchemy Pb1200 Board\n"); bcsr_init(PB1200_BCSR_PHYS_ADDR, PB1200_BCSR_PHYS_ADDR + PB1200_BCSR_HEXLED_OFS); #if 0 { u32 pin_func; /* * Enable PSC1 SYNC for AC97. Normaly done in audio driver, * but it is board specific code, so put it here. */ pin_func = au_readl(SYS_PINFUNC); au_sync(); pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1; au_writel(pin_func, SYS_PINFUNC); au_writel(0, (u32)bcsr | 0x10); /* turn off PCMCIA power */ au_sync(); } #endif #if defined(CONFIG_I2C_AU1550) { u32 freq0, clksrc; u32 pin_func; /* Select SMBus in CPLD */ bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0); pin_func = au_readl(SYS_PINFUNC); au_sync(); pin_func &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B); /* Set GPIOs correctly */ pin_func |= 2 << 17; au_writel(pin_func, SYS_PINFUNC); au_sync(); /* The I2C driver depends on 50 MHz clock */ freq0 = au_readl(SYS_FREQCTRL0); au_sync(); freq0 &= ~(SYS_FC_FRDIV1_MASK | SYS_FC_FS1 | SYS_FC_FE1); freq0 |= 3 << SYS_FC_FRDIV1_BIT; /* 396 MHz / (3 + 1) * 2 == 49.5 MHz */ au_writel(freq0, SYS_FREQCTRL0); au_sync(); freq0 |= SYS_FC_FE1; au_writel(freq0, SYS_FREQCTRL0); au_sync(); clksrc = au_readl(SYS_CLKSRC); au_sync(); clksrc &= ~(SYS_CS_CE0 | SYS_CS_DE0 | SYS_CS_ME0_MASK); /* Bit 22 is EXTCLK0 for PSC0 */ clksrc |= SYS_CS_MUX_FQ1 << SYS_CS_ME0_BIT; au_writel(clksrc, SYS_CLKSRC); au_sync(); } #endif /* * The Pb1200 development board uses external MUX for PSC0 to * support SMB/SPI. bcsr_resets bit 12: 0=SMB 1=SPI */ #ifdef CONFIG_I2C_AU1550 bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0); #endif au_sync(); }
void __init board_setup(void) { u32 pin_func; u32 sys_freqctrl, sys_clksrc; bcsr_init(DB1000_BCSR_PHYS_ADDR, DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS); sys_clksrc = sys_freqctrl = pin_func = 0; /* Set AUX clock to 12 MHz * 8 = 96 MHz */ au_writel(8, SYS_AUXPLL); au_writel(0, SYS_PINSTATERD); udelay(100); /* GPIO201 is input for PCMCIA card detect */ /* GPIO203 is input for PCMCIA interrupt request */ alchemy_gpio_direction_input(201); alchemy_gpio_direction_input(203); #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) /* Zero and disable FREQ2 */ sys_freqctrl = au_readl(SYS_FREQCTRL0); sys_freqctrl &= ~0xFFF00000; au_writel(sys_freqctrl, SYS_FREQCTRL0); /* zero and disable USBH/USBD clocks */ sys_clksrc = au_readl(SYS_CLKSRC); sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK | SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK); au_writel(sys_clksrc, SYS_CLKSRC); sys_freqctrl = au_readl(SYS_FREQCTRL0); sys_freqctrl &= ~0xFFF00000; sys_clksrc = au_readl(SYS_CLKSRC); sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK | SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK); /* FREQ2 = aux/2 = 48 MHz */ sys_freqctrl |= (0 << SYS_FC_FRDIV2_BIT) | SYS_FC_FE2 | SYS_FC_FS2; au_writel(sys_freqctrl, SYS_FREQCTRL0); /* * Route 48MHz FREQ2 into USB Host and/or Device */ sys_clksrc |= SYS_CS_MUX_FQ2 << SYS_CS_MUH_BIT; au_writel(sys_clksrc, SYS_CLKSRC); pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_USB; /* 2nd USB port is USB host */ pin_func |= SYS_PF_USB; au_writel(pin_func, SYS_PINFUNC); #endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */ #ifdef CONFIG_PCI /* Setup PCI bus controller */ au_writel(0, Au1500_PCI_CMEM); au_writel(0x00003fff, Au1500_CFG_BASE); #if defined(__MIPSEB__) au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG); #else au_writel(0xf, Au1500_PCI_CFG); #endif au_writel(0xf0000000, Au1500_PCI_MWMASK_DEV); au_writel(0, Au1500_PCI_MWBASE_REV_CCL); au_writel(0x02a00356, Au1500_PCI_STATCMD); au_writel(0x00003c04, Au1500_PCI_HDRTYPE); au_writel(0x00000008, Au1500_PCI_MBAR); au_sync(); #endif /* Enable sys bus clock divider when IDLE state or no bus activity. */ au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL); /* Enable the RTC if not already enabled */ if (!(au_readl(0xac000028) & 0x20)) { printk(KERN_INFO "enabling clock ...\n"); au_writel((au_readl(0xac000028) | 0x20), 0xac000028); } /* Put the clock in BCD mode */ if (au_readl(0xac00002c) & 0x4) { /* reg B */ au_writel(au_readl(0xac00002c) & ~0x4, 0xac00002c); au_sync(); } }