static int bfin_miiphy_read(const char *devname, uchar addr, uchar reg, ushort *val) { if (bfin_miiphy_wait()) return 1; bfin_write_EMAC_STAADD(SET_PHYAD(addr) | SET_REGAD(reg) | STABUSY); if (bfin_miiphy_wait()) return 1; *val = bfin_read_EMAC_STADAT(); return 0; }
static int bfin_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg) { ushort val = 0; if (bfin_miiphy_wait()) return 1; bfin_write_EMAC_STAADD(SET_PHYAD(addr) | SET_REGAD(reg) | STABUSY); if (bfin_miiphy_wait()) return 1; val = bfin_read_EMAC_STADAT(); return val; }
static int bfin_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg, u16 val) { if (bfin_miiphy_wait()) return 1; bfin_write_EMAC_STADAT(val); bfin_write_EMAC_STAADD(SET_PHYAD(addr) | SET_REGAD(reg) | STAOP | STABUSY); return 0; }
static int bfin_EMAC_init(struct eth_device *dev, bd_t *bd) { u32 opmode; int dat; int i; debug("Eth_init: ......\n"); txIdx = 0; rxIdx = 0; /* Initialize System Register */ if (bfin_miiphy_init(dev, &dat) < 0) return -1; /* Initialize EMAC address */ bfin_EMAC_setup_addr(dev); /* Initialize TX and RX buffer */ for (i = 0; i < PKTBUFSRX; i++) { rxbuf[i] = SetupRxBuffer(i); if (i > 0) { rxbuf[i - 1]->Dma[1].NEXT_DESC_PTR = rxbuf[i]->Dma; if (i == (PKTBUFSRX - 1)) rxbuf[i]->Dma[1].NEXT_DESC_PTR = rxbuf[0]->Dma; } } for (i = 0; i < TX_BUF_CNT; i++) { txbuf[i] = SetupTxBuffer(i); if (i > 0) { txbuf[i - 1]->Dma[1].NEXT_DESC_PTR = txbuf[i]->Dma; if (i == (TX_BUF_CNT - 1)) txbuf[i]->Dma[1].NEXT_DESC_PTR = txbuf[0]->Dma; } } /* Set RX DMA */ bfin_write_DMA1_NEXT_DESC_PTR(rxbuf[0]->Dma); bfin_write_DMA1_CONFIG(rxbuf[0]->Dma[0].CONFIG_DATA); /* Wait MII done */ bfin_miiphy_wait(); /* We enable only RX here */ /* ASTP : Enable Automatic Pad Stripping PR : Promiscuous Mode for test PSF : Receive frames with total length less than 64 bytes. FDMODE : Full Duplex Mode LB : Internal Loopback for test RE : Receiver Enable */ if (dat == FDMODE) opmode = ASTP | FDMODE | PSF; else opmode = ASTP | PSF; opmode |= RE; #ifdef CONFIG_RMII opmode |= TE | RMII; #endif /* Turn on the EMAC */ bfin_write_EMAC_OPMODE(opmode); return 0; }