void
hubii_eint_init(cnodeid_t cnode)
{
int bit, rv;
ii_iidsr_u_t hubio_eint;
hubinfo_t hinfo;
cpuid_t intr_cpu;
devfs_handle_t hub_v;
ii_ilcsr_u_t ilcsr;
int bit_pos_to_irq(int bit);
int synergy_intr_connect(int bit, int cpuid);
hub_v = (devfs_handle_t)cnodeid_to_vertex(cnode);
ASSERT_ALWAYS(hub_v);
hubinfo_get(hub_v, &hinfo);
ASSERT(hinfo);
ASSERT(hinfo->h_cnodeid == cnode);
ilcsr.ii_ilcsr_regval = REMOTE_HUB_L(hinfo->h_nasid, IIO_ILCSR);
if ((ilcsr.ii_ilcsr_fld_s.i_llp_stat & 0x2) == 0) {
/*
* HUB II link is not up.
* Just disable LLP, and don't connect any interrupts.
*/
ilcsr.ii_ilcsr_fld_s.i_llp_en = 0;
REMOTE_HUB_S(hinfo->h_nasid, IIO_ILCSR, ilcsr.ii_ilcsr_regval);
return;
}
/* Select a possible interrupt target where there is a free interrupt
* bit and also reserve the interrupt bit for this IO error interrupt
*/
intr_cpu = intr_heuristic(hub_v,0,INTRCONNECT_ANYBIT,II_ERRORINT,hub_v,
"HUB IO error interrupt",&bit);
if (intr_cpu == CPU_NONE) {
printk("hubii_eint_init: intr_reserve_level failed, cnode %d", cnode);
return;
}
rv = intr_connect_level(intr_cpu, bit, 0, NULL);
synergy_intr_connect(bit, intr_cpu);
request_irq(bit_pos_to_irq(bit) + (intr_cpu << 8), hubii_eint_handler, 0, "SN hub error", (void *)hub_v);
ASSERT_ALWAYS(rv >= 0);
hubio_eint.ii_iidsr_regval = 0;
hubio_eint.ii_iidsr_fld_s.i_enable = 1;
hubio_eint.ii_iidsr_fld_s.i_level = bit;/* Take the least significant bits*/
hubio_eint.ii_iidsr_fld_s.i_node = COMPACT_TO_NASID_NODEID(cnode);
hubio_eint.ii_iidsr_fld_s.i_pi_id = cpuid_to_subnode(intr_cpu);
REMOTE_HUB_S(hinfo->h_nasid, IIO_IIDSR, hubio_eint.ii_iidsr_regval);
}
int
synergy_intr_connect(int bit,
int cpuid)
{
int irq;
unsigned is_b;
irq = bit_pos_to_irq(bit);
is_b = (cpuid_to_slice(cpuid)) & 1;
if (is_b) {
setclear_mask_b(irq,cpuid,1);
setclear_mask_a(irq,cpuid, 0);
} else {
setclear_mask_a(irq, cpuid, 1);
setclear_mask_b(irq, cpuid, 0);
}
return 0;
}
int
sn1_request_irq (unsigned int requested_irq, void (*handler)(int, void *, struct pt_regs *),
unsigned long irqflags, const char * devname, void *dev_id)
{
devfs_handle_t curr_dev;
devfs_handle_t dev;
pciio_intr_t intr_handle;
pciio_intr_line_t line;
device_desc_t dev_desc;
int cpuid, bit, cnode;
struct sn1_intr_action *ap, *new_ap;
struct sn1_cnode_action_list *alp;
int irq;
if ( (requested_irq & 0xff) == 0 ) {
int ret;
sgi_pci_intr_support(requested_irq,
&dev_desc, &dev, &line, &curr_dev);
intr_handle = pciio_intr_alloc(curr_dev, NULL, line, curr_dev);
bit = intr_handle->pi_irq;
cpuid = intr_handle->pi_cpu;
irq = bit_pos_to_irq(bit);
cnode = cpuid_to_cnodeid(cpuid);
new_ap = (struct sn1_intr_action *)kmalloc(
sizeof(struct sn1_intr_action), GFP_KERNEL);
irq_desc[irq].status = 0;
new_ap->handler = handler;
new_ap->intr_arg = dev_id;
new_ap->flags = irqflags;
new_ap->next = NULL;
alp = sn1_node_actions[cnode];
spin_lock(&alp[irq].action_list_lock);
ap = alp[irq].action_list;
/* check action list for "share" consistency */
while (ap){
if (!(ap->flags & irqflags & SA_SHIRQ) ) {
return(-EBUSY);
spin_unlock(&alp[irq].action_list_lock);
}
ap = ap->next;
}
ap = alp[irq].action_list;
if (ap) {
while (ap->next) {
ap = ap->next;
}
ap->next = new_ap;
} else {
alp[irq].action_list = new_ap;
}
ret = pciio_intr_connect(intr_handle, (intr_func_t)handler, dev_id, NULL);
if (ret) { /* connect failed, undo what we did. */
new_ap = alp[irq].action_list;
if (new_ap == ap) {
alp[irq].action_list = NULL;
kfree(ap);
} else {
while (new_ap->next && new_ap->next != ap) {
new_ap = new_ap->next;
}
if (new_ap->next == ap) {
new_ap->next = ap->next;
kfree(ap);
}
}
}
spin_unlock(&alp[irq].action_list_lock);
return(ret);
} else {
return(request_irq(requested_irq, handler, irqflags, devname, dev_id));
}
}
/*
* sn_pci_fixup() - This routine is called when platform_pci_fixup() is
* invoked at the end of pcibios_init() to link the Linux pci
* infrastructure to SGI IO Infrasturcture - ia64/kernel/pci.c
*
* Other platform specific fixup can also be done here.
*/
void
sn_pci_fixup(int arg)
{
struct list_head *ln;
struct pci_bus *pci_bus = NULL;
struct pci_dev *device_dev = NULL;
struct sn_widget_sysdata *widget_sysdata;
struct sn_device_sysdata *device_sysdata;
#ifdef SN_IOPORTS
unsigned long ioport;
#endif
pciio_intr_t intr_handle;
int cpuid, bit;
devfs_handle_t device_vertex;
pciio_intr_line_t lines;
extern void sn_pci_find_bios(void);
#ifdef CONFIG_IA64_SGI_SN2
extern int numnodes;
int cnode;
#endif /* CONFIG_IA64_SGI_SN2 */
if (arg == 0) {
sn_init_irq_desc();
sn_pci_find_bios();
#ifdef CONFIG_IA64_SGI_SN2
for (cnode = 0; cnode < numnodes; cnode++) {
extern void intr_init_vecblk(nodepda_t *npda, cnodeid_t, int);
intr_init_vecblk(NODEPDA(cnode), cnode, 0);
}
#endif /* CONFIG_IA64_SGI_SN2 */
return;
}
#if 0
{
devfs_handle_t bridge_vhdl = pci_bus_to_vertex(0);
pcibr_soft_t pcibr_soft = (pcibr_soft_t) hwgraph_fastinfo_get(bridge_vhdl);
bridge_t *bridge = pcibr_soft->bs_base;
printk("pci_fixup_ioc3: Before devreg fixup\n");
printk("pci_fixup_ioc3: Devreg 0 0x%x\n", bridge->b_device[0].reg);
printk("pci_fixup_ioc3: Devreg 1 0x%x\n", bridge->b_device[1].reg);
printk("pci_fixup_ioc3: Devreg 2 0x%x\n", bridge->b_device[2].reg);
printk("pci_fixup_ioc3: Devreg 3 0x%x\n", bridge->b_device[3].reg);
printk("pci_fixup_ioc3: Devreg 4 0x%x\n", bridge->b_device[4].reg);
printk("pci_fixup_ioc3: Devreg 5 0x%x\n", bridge->b_device[5].reg);
printk("pci_fixup_ioc3: Devreg 6 0x%x\n", bridge->b_device[6].reg);
printk("pci_fixup_ioc3: Devreg 7 0x%x\n", bridge->b_device[7].reg);
}
#endif
done_probing = 1;
/*
* Initialize the pci bus vertex in the pci_bus struct.
*/
for( ln = pci_root_buses.next; ln != &pci_root_buses; ln = ln->next) {
pci_bus = pci_bus_b(ln);
widget_sysdata = kmalloc(sizeof(struct sn_widget_sysdata),
GFP_KERNEL);
widget_sysdata->vhdl = pci_bus_to_vertex(pci_bus->number);
pci_bus->sysdata = (void *)widget_sysdata;
}
/*
* set the root start and end so that drivers calling check_region()
* won't see a conflict
*/
#ifdef SN_IOPORTS
ioport_resource.start = sn_ioport_num;
ioport_resource.end = 0xffff;
#else
#if defined(CONFIG_IA64_SGI_SN1)
if ( IS_RUNNING_ON_SIMULATOR() ) {
/*
* IDE legacy IO PORTs are supported in Medusa.
* Just open up IO PORTs from 0 .. ioport_resource.end.
*/
ioport_resource.start = 0;
} else {
/*
* We do not support Legacy IO PORT numbers.
*/
ioport_resource.start |= IO_SWIZ_BASE | __IA64_UNCACHED_OFFSET;
}
ioport_resource.end |= (HSPEC_SWIZ_BASE-1) | __IA64_UNCACHED_OFFSET;
#else
// Need something here for sn2.... ZXZXZX
#endif
#endif
/*
* Set the root start and end for Mem Resource.
*/
iomem_resource.start = 0;
iomem_resource.end = 0xffffffffffffffff;
/*
* Initialize the device vertex in the pci_dev struct.
*/
pci_for_each_dev(device_dev) {
unsigned int irq;
int idx;
u16 cmd;
devfs_handle_t vhdl;
unsigned long size;
extern int bit_pos_to_irq(int);
if (device_dev->vendor == PCI_VENDOR_ID_SGI &&
device_dev->device == PCI_DEVICE_ID_SGI_IOC3) {
extern void pci_fixup_ioc3(struct pci_dev *d);
pci_fixup_ioc3(device_dev);
}
/* Set the device vertex */
device_sysdata = kmalloc(sizeof(struct sn_device_sysdata),
GFP_KERNEL);
device_sysdata->vhdl = devfn_to_vertex(device_dev->bus->number, device_dev->devfn);
device_sysdata->isa64 = 0;
/*
* Set the xbridge Device(X) Write Buffer Flush and Xbow Flush
* register addresses.
*/
(void) set_flush_addresses(device_dev, device_sysdata);
device_dev->sysdata = (void *) device_sysdata;
set_sn_pci64(device_dev);
pci_read_config_word(device_dev, PCI_COMMAND, &cmd);
/*
* Set the resources address correctly. The assumption here
* is that the addresses in the resource structure has been
* read from the card and it was set in the card by our
* Infrastructure ..
*/
vhdl = device_sysdata->vhdl;
for (idx = 0; idx < PCI_ROM_RESOURCE; idx++) {
size = 0;
size = device_dev->resource[idx].end -
device_dev->resource[idx].start;
if (size) {
device_dev->resource[idx].start = (unsigned long)pciio_pio_addr(vhdl, 0, PCIIO_SPACE_WIN(idx), 0, size, 0, PCIIO_BYTE_STREAM);
device_dev->resource[idx].start |= __IA64_UNCACHED_OFFSET;
}
else
continue;
device_dev->resource[idx].end =
device_dev->resource[idx].start + size;
#ifdef CONFIG_IA64_SGI_SN1
/*
* Adjust the addresses to go to the SWIZZLE ..
*/
device_dev->resource[idx].start =
device_dev->resource[idx].start & 0xfffff7ffffffffff;
device_dev->resource[idx].end =
device_dev->resource[idx].end & 0xfffff7ffffffffff;
#endif
if (device_dev->resource[idx].flags & IORESOURCE_IO) {
cmd |= PCI_COMMAND_IO;
#ifdef SN_IOPORTS
ioport = sn_allocate_ioports(device_dev->resource[idx].start);
if (ioport < 0) {
printk("sn_pci_fixup: PCI Device 0x%x on PCI Bus %d not mapped to IO PORTs .. IO PORTs exhausted\n", device_dev->devfn, device_dev->bus->number);
continue;
}
pciio_config_set(vhdl, (unsigned) PCI_BASE_ADDRESS_0 + (idx * 4), 4, (res + (ioport & 0xfff)));
printk("sn_pci_fixup: ioport number %d mapped to pci address 0x%lx\n", ioport, (res + (ioport & 0xfff)));
device_dev->resource[idx].start = ioport;
device_dev->resource[idx].end = ioport + SN_IOPORTS_UNIT;
#endif
}
if (device_dev->resource[idx].flags & IORESOURCE_MEM)
cmd |= PCI_COMMAND_MEMORY;
}
/*
* Now handle the ROM resource ..
*/
size = device_dev->resource[PCI_ROM_RESOURCE].end -
device_dev->resource[PCI_ROM_RESOURCE].start;
if (size) {
device_dev->resource[PCI_ROM_RESOURCE].start =
(unsigned long) pciio_pio_addr(vhdl, 0, PCIIO_SPACE_ROM, 0,
size, 0, PCIIO_BYTE_STREAM);
device_dev->resource[PCI_ROM_RESOURCE].start |= __IA64_UNCACHED_OFFSET;
device_dev->resource[PCI_ROM_RESOURCE].end =
device_dev->resource[PCI_ROM_RESOURCE].start + size;
#ifdef CONFIG_IA64_SGI_SN1
/*
* go through synergy swizzled space
*/
device_dev->resource[PCI_ROM_RESOURCE].start &= 0xfffff7ffffffffffUL;
device_dev->resource[PCI_ROM_RESOURCE].end &= 0xfffff7ffffffffffUL;
#endif
}
/*
* Update the Command Word on the Card.
*/
cmd |= PCI_COMMAND_MASTER; /* If the device doesn't support */
/* bit gets dropped .. no harm */
pci_write_config_word(device_dev, PCI_COMMAND, cmd);
pci_read_config_byte(device_dev, PCI_INTERRUPT_PIN, (unsigned char *)&lines);
if (device_dev->vendor == PCI_VENDOR_ID_SGI &&
device_dev->device == PCI_DEVICE_ID_SGI_IOC3 ) {
lines = 1;
}
device_sysdata = (struct sn_device_sysdata *)device_dev->sysdata;
device_vertex = device_sysdata->vhdl;
intr_handle = pciio_intr_alloc(device_vertex, NULL, lines, device_vertex);
bit = intr_handle->pi_irq;
cpuid = intr_handle->pi_cpu;
#ifdef CONFIG_IA64_SGI_SN1
irq = bit_pos_to_irq(bit);
#else /* SN2 */
irq = bit;
#endif
irq = irq + (cpuid << 8);
pciio_intr_connect(intr_handle);
device_dev->irq = irq;
#ifdef ajmtestintr
{
int slot = PCI_SLOT(device_dev->devfn);
static int timer_set = 0;
pcibr_intr_t pcibr_intr = (pcibr_intr_t)intr_handle;
pcibr_soft_t pcibr_soft = pcibr_intr->bi_soft;
extern void intr_test_handle_intr(int, void*, struct pt_regs *);
if (!timer_set) {
intr_test_set_timer();
timer_set = 1;
}
intr_test_register_irq(irq, pcibr_soft, slot);
request_irq(irq, intr_test_handle_intr,0,NULL, NULL);
}
#endif
}
#if 0
{
devfs_handle_t bridge_vhdl = pci_bus_to_vertex(0);
pcibr_soft_t pcibr_soft = (pcibr_soft_t) hwgraph_fastinfo_get(bridge_vhdl);
bridge_t *bridge = pcibr_soft->bs_base;
printk("pci_fixup_ioc3: Before devreg fixup\n");
printk("pci_fixup_ioc3: Devreg 0 0x%x\n", bridge->b_device[0].reg);
printk("pci_fixup_ioc3: Devreg 1 0x%x\n", bridge->b_device[1].reg);
printk("pci_fixup_ioc3: Devreg 2 0x%x\n", bridge->b_device[2].reg);
printk("pci_fixup_ioc3: Devreg 3 0x%x\n", bridge->b_device[3].reg);
printk("pci_fixup_ioc3: Devreg 4 0x%x\n", bridge->b_device[4].reg);
printk("pci_fixup_ioc3: Devreg 5 0x%x\n", bridge->b_device[5].reg);
printk("pci_fixup_ioc3: Devreg 6 0x%x\n", bridge->b_device[6].reg);
printk("pci_fixup_ioc3: Devreg 7 0x%x\n", bridge->b_device[7].reg);
}
printk("testing Big Window: 0xC0000200c0000000 %p\n", *( (volatile uint64_t *)0xc0000200a0000000));
printk("testing Big Window: 0xC0000200c0000008 %p\n", *( (volatile uint64_t *)0xc0000200a0000008));
#endif
}
