示例#1
0
void mbx_init(void)
{
    volatile immap_t *immr = (immap_t *)CFG_IMMR;
    volatile memctl8xx_t *memctl = &immr->im_memctl;
    ulong speed, refclock, plprcr, sccr;

    /* real-time clock status and control register */
    immr->im_sitk.sitk_rtcsck = KAPWR_KEY;
    immr->im_sit.sit_rtcsc = 0x00C3;

    /* SIEL and SIMASK Registers (see MBX PRG 2-3) */
    immr->im_siu_conf.sc_simask = 0x00000000;
    immr->im_siu_conf.sc_siel = 0xAAAA0000;
    immr->im_siu_conf.sc_tesr = 0xFFFFFFFF;

    /*
     * Prepare access to i2c bus. The MBX offers 3 devices on the i2c
     * bus:
     * 1. Vital Product Data (contains clock speeds, mac-address etc,
     *    see vpd.h)
     * 2. RAM Specs (see dimm.h)
     * 2. DIMM Specs (see dimm.h)
     */
    vpd_init();

    /* system clock and reset control register */
    immr->im_clkrstk.cark_sccrk = KAPWR_KEY;
    sccr = immr->im_clkrst.car_sccr;
    sccr &= SCCR_MASK;
    sccr |= CFG_SCCR;
    immr->im_clkrst.car_sccr = sccr;

    speed = board_get_cpufreq();
    refclock = get_reffreq();

    plprcr = CFG_PLPRCR;
    plprcr |= ((speed + refclock / 2) / refclock - 1) << 20;
    immr->im_clkrst.car_plprcr = plprcr;

    /*
     * preliminary setup of memory controller:
     * - map pci registers
     * - map configuation and status registers
     * - DON'T map ram/flash/rom yet, this is done in initdram()
     */
    switch(speed / 1000000)
    {
    case 40:
        memctl->memc_br4 = CFG_NVRAM_BASE | 0x401;
        memctl->memc_or4 = CFG_NVRAM_OR   | 0x920;
        break;
    case 50:
        memctl->memc_br4 = CFG_NVRAM_BASE | 0x401;
        memctl->memc_or4 = CFG_NVRAM_OR   | 0x930;
        break;
    default:
        hang();
        break;
    }
    memctl->memc_br5 = CFG_PCIMEM_BASE | 0x001;
    memctl->memc_or5 = CFG_PCIMEM_OR;
    memctl->memc_br6 = CFG_PCIBRIDGE_BASE | 0x001;
    memctl->memc_or6 = CFG_PCIBRIDGE_OR;
}
示例#2
0
long int initdram (int board_type)
{
    volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
    volatile memctl8xx_t *memctl = &immap->im_memctl;
    unsigned long ram_sz = 0;
    unsigned long dimm_sz = 0;
    dimm_t vpd_dimm, vpd_dram;
    unsigned int speed = board_get_cpufreq() / 1000000;

    if (vpd_read(0xa2, (uchar*)&vpd_dimm, sizeof(vpd_dimm), 0) > 0)
    {
        dimm_sz = get_ramsize(&vpd_dimm);
    }
    if (vpd_read(0xa6, (uchar*)&vpd_dram, sizeof(vpd_dram), 0) > 0)
    {
        ram_sz = get_ramsize(&vpd_dram);
    }

    /*
     * Only initialize memory controller when running from FLASH.
     * When running from RAM, don't touch it.
     */
    if ((ulong)initdram & 0xff000000)
    {
        ulong dimm_bank;
        ulong br0_32 = memctl->memc_br0 & 0x400;

        switch(speed)
        {
        case 40:
            upmconfig(UPMA, (uint *)sdram_table_40,
                      sizeof(sdram_table_40) / sizeof(uint));
            memctl->memc_mptpr = 0x0200;
            memctl->memc_mamr = dimm_sz ? 0x06801000 : 0x13801000;
            memctl->memc_br0 = 0xfe000000 | br0_32            | 1;
            memctl->memc_or0 = 0xff800930;
            memctl->memc_br7 = 0xfc000000 | (br0_32 ^ br0_32) | 1;
            memctl->memc_or7 = 0xff800930;
            break;
        case 50:
            upmconfig(UPMA, (uint *)sdram_table_50,
                      sizeof(sdram_table_50) / sizeof(uint));
            memctl->memc_mptpr = 0x0200;
            memctl->memc_mamr = dimm_sz ? 0x08801000 : 0x1880100;
            memctl->memc_br0 = 0xfe000000 |  br0_32           | 1;
            memctl->memc_or0 = 0xff800940;
            memctl->memc_br7 = 0xfc000000 | (br0_32 ^ br0_32) | 1;
            memctl->memc_or7 = 0xff800940;
            break;
        default:
            hang();
            break;
        }

        /* now map ram and dimm, largest one first */
        dimm_bank = dimm_sz / 2;
        if (!dimm_sz)
        {
            memctl->memc_br1 = CFG_SDRAM_BASE  | 0x81;
            memctl->memc_or1 = ~(ram_sz - 1)   | 0x400;
            memctl->memc_br2 = 0;
            memctl->memc_br3 = 0;
        }
        else if (ram_sz > dimm_bank)
        {
            memctl->memc_br1 = CFG_SDRAM_BASE  | 0x81;
            memctl->memc_or1 = ~(ram_sz - 1)   | 0x400;
            memctl->memc_br2 = (CFG_SDRAM_BASE + ram_sz) | 0x81;
            memctl->memc_or2 = ~(dimm_bank - 1)          | 0x400;
            memctl->memc_br3 = (CFG_SDRAM_BASE + ram_sz + dimm_bank) | 0x81;
            memctl->memc_or3 = ~(dimm_bank - 1)                      | 0x400;
        }
        else
        {
            memctl->memc_br2 = CFG_SDRAM_BASE   | 0x81;
            memctl->memc_or2 = ~(dimm_bank - 1) | 0x400;
            memctl->memc_br3 = (CFG_SDRAM_BASE + dimm_bank) | 0x81;
            memctl->memc_or3 = ~(dimm_bank - 1)             | 0x400;
            memctl->memc_br1 = (CFG_SDRAM_BASE + dimm_sz) | 0x81;
            memctl->memc_or1 = ~(ram_sz - 1)              | 0x400;
        }
    }

    return ram_sz + dimm_sz;
}
示例#3
0
文件: mbx8xx.c 项目: Brian1013/u-boot
void mbx_init (void)
{
	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
	volatile memctl8xx_t *memctl = &immr->im_memctl;
	ulong speed, plprcr, sccr;
	ulong br0_32 = memctl->memc_br0 & 0x400;

	/* real-time clock status and control register */
	immr->im_sitk.sitk_rtcsck = KAPWR_KEY;
	immr->im_sit.sit_rtcsc = 0x00C3;

	/* SIEL and SIMASK Registers (see MBX PRG 2-3) */
	immr->im_siu_conf.sc_simask = 0x00000000;
	immr->im_siu_conf.sc_siel = 0xAAAA0000;
	immr->im_siu_conf.sc_tesr = 0xFFFFFFFF;

	/*
	 * Prepare access to i2c bus. The MBX offers 3 devices on the i2c bus:
	 * 1. Vital Product Data (contains clock speeds, MAC address etc, see vpd.h)
	 * 2. RAM  Specs (see dimm.h)
	 * 2. DIMM Specs (see dimm.h)
	 */
	vpd_init ();

	/* system clock and reset control register */
	immr->im_clkrstk.cark_sccrk = KAPWR_KEY;
	sccr = immr->im_clkrst.car_sccr;
	sccr &= SCCR_MASK;
	sccr |= CONFIG_SYS_SCCR;
	immr->im_clkrst.car_sccr = sccr;

	speed = board_get_cpufreq ();

#if ((CONFIG_SYS_PLPRCR & PLPRCR_MF_MSK) != 0)
	plprcr = CONFIG_SYS_PLPRCR;
#else
	plprcr = immr->im_clkrst.car_plprcr;
	plprcr &= PLPRCR_MF_MSK;	/* isolate MF field */
	plprcr |= CONFIG_SYS_PLPRCR;		/* reset control bits   */
#endif

#ifdef CONFIG_SYS_USE_OSCCLK			/* See doc/README.MBX ! */
	plprcr |= ((speed + get_reffreq() / 2) / refclock - 1) << 20;
#endif

	immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
	immr->im_clkrst.car_plprcr = plprcr;

	/*
	 * preliminary setup of memory controller:
	 * - map Flash, otherwise configuration/status
	 *    registers won't be accessible when read
	 *    by board_init_f.
	 * - map NVRAM and configuation/status registers.
	 * - map pci registers.
	 * - DON'T map ram yet, this is done in initdram().
	 */
	switch (speed / 1000000) {
	case 40:
		memctl->memc_br0 = 0xFE000000 | br0_32 | 1;
		memctl->memc_or0 = 0xFF800930;
		memctl->memc_or4 = CONFIG_SYS_NVRAM_OR | 0x920;
		memctl->memc_br4 = CONFIG_SYS_NVRAM_BASE | 0x401;
		break;
	case 50:
		memctl->memc_br0 = 0xFE000000 | br0_32 | 1;
		memctl->memc_or0 = 0xFF800940;
		memctl->memc_or4 = CONFIG_SYS_NVRAM_OR | 0x930;
		memctl->memc_br4 = CONFIG_SYS_NVRAM_BASE | 0x401;
		break;
	default:
		hang ();
		break;
	}
#ifdef CONFIG_USE_PCI
	memctl->memc_or5 = CONFIG_SYS_PCIMEM_OR;
	memctl->memc_br5 = CONFIG_SYS_PCIMEM_BASE | 0x001;
	memctl->memc_or6 = CONFIG_SYS_PCIBRIDGE_OR;
	memctl->memc_br6 = CONFIG_SYS_PCIBRIDGE_BASE | 0x001;
#endif
	/*
	 * FIXME: I do not understand why I have to call this to
	 * initialise the control register here before booting from
	 * the PCMCIA card but if I do not the Linux kernel falls
	 * over in a big heap. If you can answer this question I
	 * would like to know about it.
	 */
	board_ether_init();
}