int board_init(void) { /* Power up base board */ sc_pm_set_resource_power_mode(-1, SC_R_BOARD_R1, SC_PM_PW_MODE_ON); board_gpio_init(); return 0; }
int exynos_init(void) { /* The last MB of memory is reserved for secure firmware */ gd->ram_size -= SZ_1M; gd->bd->bi_dram[CONFIG_NR_DRAM_BANKS - 1].size -= SZ_1M; board_gpio_init(); return 0; }
/************************************************************************************ * Name: board_on_reset * * Description: * Optionally provided function called on entry to board_system_reset * It should perform any house keeping prior to the rest. * * status - 1 if resetting to boot loader * 0 if just resetting * ************************************************************************************/ __EXPORT void board_on_reset(int status) { /* configure the GPIO pins to outputs and keep them low */ const uint32_t gpio[] = PX4_GPIO_PWM_INIT_LIST; board_gpio_init(gpio, arraySize(gpio)); if (status >= 0) { up_mdelay(6); } }
int board_early_init_f(void) { ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); setbits_be32(&gur->pmuxcr, (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP)); clrbits_be32(&gur->sdhcdcr, SDHCDCR_CD_INV); clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA); setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TDM_ENA); board_gpio_init(); board_cpld_init(); return 0; }
__EXPORT void stm32_boardinitialize(void) { board_on_reset(-1); /* Reset PWM first thing */ /* configure LEDs */ board_autoled_initialize(); /* configure pins */ const uint32_t gpio[] = PX4_GPIO_INIT_LIST; board_gpio_init(gpio, arraySize(gpio)); /* configure SPI interfaces */ stm32_spiinitialize(); /* configure USB interfaces */ stm32_usbinitialize(); }
void dm36x_lowlevel_init(ulong bootflag) { struct davinci_uart_ctrl_regs *davinci_uart_ctrl_regs = (struct davinci_uart_ctrl_regs *)(CONFIG_SYS_NS16550_COM1 + DAVINCI_UART_CTRL_BASE); /* Mask all interrupts */ writel(DV_AINTC_INTCTL_IDMODE, &dv_aintc_regs->intctl); writel(0x0, &dv_aintc_regs->eabase); writel(0x0, &dv_aintc_regs->eint0); writel(0x0, &dv_aintc_regs->eint1); /* Clear all interrupts */ writel(0xffffffff, &dv_aintc_regs->fiq0); writel(0xffffffff, &dv_aintc_regs->fiq1); writel(0xffffffff, &dv_aintc_regs->irq0); writel(0xffffffff, &dv_aintc_regs->irq1); dm365_por_reset(); dm365_wdt_reset(); /* System PSC setup - enable all */ dm365_psc_init(); /* Setup Pinmux */ dm365_pinmux_ctl(0, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX0); dm365_pinmux_ctl(1, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX1); dm365_pinmux_ctl(2, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX2); dm365_pinmux_ctl(3, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX3); dm365_pinmux_ctl(4, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX4); /* PLL setup */ dm365_pll1_init(CONFIG_SYS_DM36x_PLL1_PLLM, CONFIG_SYS_DM36x_PLL1_PREDIV); dm365_pll2_init(CONFIG_SYS_DM36x_PLL2_PLLM, CONFIG_SYS_DM36x_PLL2_PREDIV); /* GPIO setup */ board_gpio_init(); NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1), CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); /* * Fix Power and Emulation Management Register * see sprufh2.pdf page 38 Table 22 */ writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST | DAVINCI_UART_PWREMU_MGMT_UTRST), &davinci_uart_ctrl_regs->pwremu_mgmt); puts("ddr init\n"); dm365_ddr_setup(); puts("emif init\n"); dm365_emif_init(); dm365_wdt_flag_on(); #if defined(CONFIG_POST) /* * Do memory tests, calls arch_memory_failure_handle() * if error detected. */ memory_post_test(0); #endif }
int exynos_init(void) { board_gpio_init(); return 0; }