static void arm_sysctl_gpio_set(void *opaque, int line, int level)
{
arm_sysctl_state *s = (arm_sysctl_state *)opaque;
switch (line) {
case ARM_SYSCTL_GPIO_MMC_WPROT:
{
/* For PB926 and EB write-protect is bit 2 of SYS_MCI;
* for all later boards it is bit 1.
*/
int bit = 2;
if ((board_id(s) == BOARD_ID_PB926) || (board_id(s) == BOARD_ID_EB)) {
bit = 4;
}
s->sys_mci &= ~bit;
if (level) {
s->sys_mci |= bit;
}
break;
}
case ARM_SYSCTL_GPIO_MMC_CARDIN:
s->sys_mci &= ~1;
if (level) {
s->sys_mci |= 1;
}
break;
}
}
/**
* Add coreboot tables, CBMEM information and optional board specific strapping
* IDs to the device tree loaded via FIT.
*/
static void add_cb_fdt_data(struct device_tree *tree)
{
u32 addr_cells = 1, size_cells = 1;
u64 reg_addrs[2], reg_sizes[2];
void *baseptr = NULL;
size_t size = 0;
static const char *firmware_path[] = {"firmware", NULL};
struct device_tree_node *firmware_node = dt_find_node(tree->root,
firmware_path, &addr_cells, &size_cells, 1);
/* Need to add 'ranges' to the intermediate node to make 'reg' work. */
dt_add_bin_prop(firmware_node, "ranges", NULL, 0);
static const char *coreboot_path[] = {"coreboot", NULL};
struct device_tree_node *coreboot_node = dt_find_node(firmware_node,
coreboot_path, &addr_cells, &size_cells, 1);
dt_add_string_prop(coreboot_node, "compatible", "coreboot");
/* Fetch CB tables from cbmem */
void *cbtable = cbmem_find(CBMEM_ID_CBTABLE);
if (!cbtable) {
printk(BIOS_WARNING, "FIT: No coreboot table found!\n");
return;
}
/* First 'reg' address range is the coreboot table. */
const struct lb_header *header = cbtable;
reg_addrs[0] = (uintptr_t)header;
reg_sizes[0] = header->header_bytes + header->table_bytes;
/* Second is the CBMEM area (which usually includes the coreboot
table). */
cbmem_get_region(&baseptr, &size);
if (!baseptr || size == 0) {
printk(BIOS_WARNING, "FIT: CBMEM pointer/size not found!\n");
return;
}
reg_addrs[1] = (uintptr_t)baseptr;
reg_sizes[1] = size;
dt_add_reg_prop(coreboot_node, reg_addrs, reg_sizes, 2, addr_cells,
size_cells);
/* Expose board ID, SKU ID, and RAM code to payload.*/
if (board_id() != UNDEFINED_STRAPPING_ID)
dt_add_u32_prop(coreboot_node, "board-id", board_id());
if (sku_id() != UNDEFINED_STRAPPING_ID)
dt_add_u32_prop(coreboot_node, "sku-id", sku_id());
if (ram_code() != UNDEFINED_STRAPPING_ID)
dt_add_u32_prop(coreboot_node, "ram-code", ram_code());
}
void mainboard_silicon_init_params(SILICON_INIT_UPD *params)
{
if (board_id() == BOARD_BCRD2) {
params->ChvSvidConfig = SVID_PMIC_CONFIG;
params->PMIC_I2CBus = BCRD2_PMIC_I2C_BUS;
}
}
static void display_pattern(int pattern)
{
#if IS_ENABLED(notyet)
if (board_id() == BOARD_ID_WHIRLWIND_SP5)
ww_ring_display_pattern(GSBI_ID_7, pattern);
#endif
}
void mainboard_save_dimm_info(void)
{
char part_num_store[DIMM_INFO_PART_NUMBER_SIZE];
const char *part_num = NULL;
if (!IS_ENABLED(CONFIG_DRAM_PART_NUM_IN_CBI)) {
save_dimm_info_by_sku_config();
return;
}
if (!IS_ENABLED(CONFIG_DRAM_PART_NUM_ALWAYS_IN_CBI)) {
/* Fall back on part numbers encoded in lp4cfg array. */
if (board_id() < CONFIG_DRAM_PART_IN_CBI_BOARD_ID_MIN) {
save_dimm_info_by_sku_config();
return;
}
}
if (google_chromeec_cbi_get_dram_part_num(&part_num_store[0],
ARRAY_SIZE(part_num_store)) < 0)
printk(BIOS_ERR, "ERROR: Couldn't obtain DRAM part number from CBI\n");
else
part_num = &part_num_store[0];
save_lpddr4_dimm_info_part_num(part_num);
}
/*
* Configure GPIO depend on platform
*/
void mainboard_config_gpios(void)
{
size_t num;
const struct dnv_pad_config *table;
uint8_t boardid = board_id();
/* Configure pads prior to SiliconInit() in case there's any
* dependencies during hardware initialization.
*/
switch (boardid) {
case BoardIdHarcuvar:
table = harcuvar_gpio_table;
num = ARRAY_SIZE(harcuvar_gpio_table);
break;
default:
table = NULL;
num = 0;
break;
}
if ((!table) || (!num)) {
printk(BIOS_ERR, "ERROR: No valid GPIO table found!\n");
return;
}
printk(BIOS_INFO, "GPIO table: 0x%x, entry num: 0x%x!\n",
(uint32_t)table, (uint32_t)num);
gpio_configure_dnv_pads(table, num);
}
static enum dram_speeds get_sdram_index(void)
{
uint32_t id;
id = board_id();
if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN))
switch (id) {
case 0:
case 1:
case 2:
return dram_200MHz;
case 3:
return dram_666MHz_NO_ODT;
default:
return dram_800MHz;
}
if (IS_ENABLED(CONFIG_BOARD_GOOGLE_GRU))
switch (id) {
case 0:
return dram_800MHz_NO_ODT;
default:
return dram_800MHz;
}
}
void pmic_init(unsigned bus)
{
/*
* Don't need to set up VDD_CORE - already done - by OTP
* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
*/
/* Restore PMIC POR defaults, in case kernel changed 'em */
pmic_slam_defaults(bus);
/* First set VDD_CPU to 1.2V, then enable the VDD_CPU regulator. */
if (board_id() == 0)
pmic_write_reg(bus, 0x00, 0x3c, 1);
else
pmic_write_reg(bus, 0x00, 0x50, 1);
/* First set VDD_GPU to 1.0V, then enable the VDD_GPU regulator. */
pmic_write_reg(bus, 0x06, 0x28, 1);
/*
* First set +1.2V_GEN_AVDD to 1.2V, then enable the +1.2V_GEN_AVDD
* regulator.
*/
pmic_write_reg(bus, 0x12, 0x10, 1);
/*
* Panel power GPIO O4. Set mode for GPIO4 (0x0c to 7), then set
* the value (register 0x20 bit 4)
*/
pmic_write_reg(bus, 0x0c, 0x07, 0);
pmic_write_reg(bus, 0x20, 0x10, 1);
}
static void arm_sysctl_reset(DeviceState *d)
{
arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, SYS_BUS_DEVICE(d));
int i;
s->leds = 0;
s->lockval = 0;
s->cfgdata1 = 0;
s->cfgdata2 = 0;
s->flags = 0;
s->resetlevel = 0;
/* Motherboard oscillators (in Hz) */
s->mb_clock[0] = 50000000; /* Static memory clock: 50MHz */
s->mb_clock[1] = 23750000; /* motherboard CLCD clock: 23.75MHz */
s->mb_clock[2] = 24000000; /* IO FPGA peripheral clock: 24MHz */
s->mb_clock[3] = 24000000; /* IO FPGA reserved clock: 24MHz */
s->mb_clock[4] = 24000000; /* System bus global clock: 24MHz */
s->mb_clock[5] = 24000000; /* IO FPGA reserved clock: 24MHz */
/* Daughterboard oscillators: reset from property values */
for (i = 0; i < s->db_num_clocks; i++) {
s->db_clock[i] = s->db_clock_reset[i];
}
if (board_id(s) == BOARD_ID_VEXPRESS) {
/* On VExpress this register will RAZ/WI */
s->sys_clcd = 0;
} else {
/* All others: CLCDID 0x1f, indicating VGA */
s->sys_clcd = 0x1f00;
}
}
static inline uint32_t get_pwr_btn_polarity(void)
{
if (board_id() < BOARD_ID_PROTO_3)
return ACTIVE_HIGH;
return ACTIVE_LOW;
}
static void configure_vop(void)
{
write32(&rk3288_grf->iomux_lcdc, IOMUX_LCDC);
/* lcdc(vop) iodomain select 1.8V */
write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 0));
switch (board_id()) {
case 0:
rk808_configure_switch(2, 1); /* VCC18_LCD */
rk808_configure_ldo(7, 2500); /* VCC10_LCD_PWREN_H */
rk808_configure_switch(1, 1); /* VCC33_LCD */
break;
default:
gpio_output(GPIO(2, B, 5), 1); /* AVDD_1V8_DISP_EN */
rk808_configure_ldo(7, 2500); /* VCC10_LCD_PWREN_H */
gpio_output(GPIO(7, B, 6), 1); /* LCD_EN */
rk808_configure_switch(1, 1); /* VCC33_LCD */
/* enable edp HPD */
gpio_input_pulldown(GPIO(7, B, 3));
write32(&rk3288_grf->iomux_edp_hotplug, IOMUX_EDP_HOTPLUG);
break;
}
}
static int enable_lcd_vdd(void)
{
uint8_t data;
/* Set 1.20V to power AVDD_DSI_CSI */
pmic_write_reg(I2CPWR_BUS, TI65913_LDO5_VOLTAGE,
VSEL_1200, 1);
pmic_write_reg(I2CPWR_BUS, TI65913_LDO5_CTRL,
TI65913_MODE_ACTIVE_ON, 1);
/*
* Enable VDD_LCD
*
* Use different GPIO based on board id
*/
switch (board_id()) {
case BOARD_ID_PROTO_0:
/* Select PMIC GPIO_6's primary function */
pmic_read_reg(I2CPWR_BUS, TI65913_PAD2, &data);
pmic_write_reg(I2CPWR_BUS, TI65913_PAD2,
PAD2_GPIO_6_PRIMARY(data), 0);
/* Set PMIC_GPIO_6 as output */
pmic_read_reg(I2CPWR_BUS, TI65913_GPIO_DATA_DIR, &data);
pmic_write_reg(I2CPWR_BUS, TI65913_GPIO_DATA_DIR,
TI65913_GPIO_6_OUTPUT, 0);
/* Set PMIC_GPIO_6 output high */
pmic_read_reg(I2CPWR_BUS, TI65913_GPIO_DATA_OUT, &data);
pmic_write_reg(I2CPWR_BUS, TI65913_GPIO_DATA_OUT,
TI65913_GPIO_6_HIGH, 1);
break;
case BOARD_ID_PROTO_1:
case BOARD_ID_PROTO_3:
gpio_set(EN_VDD_LCD, 1);
break;
default: /* unknown board */
return -1;
}
/* wait for 2ms */
mdelay(2);
/* Enable PP1800_LCDIO to panel */
gpio_set(EN_VDD18_LCD, 1);
/* wait for 1ms */
mdelay(1);
/* Set panel EN and RST signals */
gpio_set(LCD_EN, 1); /* enable */
/* wait for min 10ms */
mdelay(10);
gpio_set(LCD_RST_L, 1); /* clear reset */
/* wait for min 3ms */
mdelay(3);
return 0;
}
/* Copy SPD data for on-board memory */
void mainboard_fill_spd_data(struct pei_data *pei_data)
{
char *spd_file;
size_t spd_file_len;
int spd_index, sku_id;
gpio_t spd_gpios[] = {
GPIO_MEM_CONFIG_0,
GPIO_MEM_CONFIG_1,
GPIO_MEM_CONFIG_2,
GPIO_MEM_CONFIG_3,
};
spd_index = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
/*
* XXX: This is incorrect usage.The Board ID should be the revision ID
* and not SKU ID but on SCRD it indicates SKU.
*/
sku_id = board_id();
printk(BIOS_INFO, "SPD index %d\n", spd_index);
printk(BIOS_INFO, "Board ID %d\n", sku_id);
/* Load SPD data from CBFS */
spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
&spd_file_len);
if (!spd_file)
die("SPD data not found.");
/* make sure we have at least one SPD in the file. */
if (spd_file_len < SPD_LEN)
die("Missing SPD data.");
/* Make sure we did not overrun the buffer */
if (spd_file_len < ((spd_index + 1) * SPD_LEN)) {
printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
spd_index = 0;
}
/* Assume same memory in both channels */
spd_index *= SPD_LEN;
memcpy(pei_data->spd_data[0][0], spd_file + spd_index, SPD_LEN);
/*
* XXX: This is incorrect usage. mem_cfg should be used here instead of
* SKU ID. The current implementation of mem_config does not
* support channel population.
*/
if (sku_id != SCRD_SKU1)
memcpy(pei_data->spd_data[1][0], spd_file + spd_index, SPD_LEN);
/* Make sure a valid SPD was found */
if (pei_data->spd_data[0][0][0] == 0)
die("Invalid SPD data.");
mainboard_print_spd_info(pei_data->spd_data[0][0]);
}
void setup_chromeos_gpios(void)
{
gpio_input(WRITE_PROTECT);
gpio_input_pullup(EC_IN_RW);
gpio_input_pullup(EC_IRQ);
gpio_input_pullup(LID);
gpio_input_pullup(POWER_BUTTON);
if (board_id() < 5)
gpio_output(EC_SUSPEND_L, 1);
}
static void configure_vop(void)
{
write32(&rk3288_grf->iomux_lcdc, IOMUX_LCDC);
/* lcdc(vop) iodomain select 1.8V */
write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 0));
/*
* BL_EN gates VCC_LCD. This might be changed in future revisions
* of the board so that the display can be stablized before we
* turn on the backlight.
*
* To minimize display corruption, turn off LCDC_BL before
* powering on the backlight.
*/
switch (board_id()) {
case 0:
gpio_output(GPIO(7, A, 3), 1);
break;
default:
gpio_output(GPIO(7, A, 2), 1);
break;
}
gpio_output(GPIO_LCDC_BL, 0);
rk808_configure_switch(1, 1); /* VCC33_LCD */
/* EDP_HPD setup */
switch (board_id()) {
case 0:
/* not present */
break;
default:
/* Unlike other Veyrons, Danger has external pull resistors on
* EDP_HPD. Default for GPIO(7, B, 3) is pull-down, set to
* float.
*/
gpio_input(GPIO(7, B, 3));
write32(&rk3288_grf->iomux_edp_hotplug, IOMUX_EDP_HOTPLUG);
break;
}
}
static void sdmmc_power(int enable)
{
switch (board_id()) {
case 0:
/* VCC33_SD is tied to VCC33_SYS and is always on */
break;
default:
rk808_configure_ldo(4, enable ? 3300 : 0); /* VCC33_SD_LDO */
rk808_configure_ldo(5, enable ? 3300 : 0); /* VCCIO_SD */
break;
}
}
const struct board_hw *board_get_hw(void)
{
int i;
uint8_t bid = board_id();
for (i = 0; i < ARRAY_SIZE(board_id_map); i++) {
if (bid == board_id_map[i].board_id)
return &(board_id_map[i].hardware);
}
return 0;
}
static void lb_board_id(struct lb_header *header)
{
#if CONFIG_BOARD_ID_AUTO || CONFIG_BOARD_ID_MANUAL
struct lb_board_id *bid;
bid = (struct lb_board_id *)lb_new_record(header);
bid->tag = LB_TAG_BOARD_ID;
bid->size = sizeof(*bid);
bid->board_id = board_id();
#endif
}
void bootblock_mainboard_init(void)
{
/* adjust gpio params when external voltage is 1.8V */
gpio_init(GPIO_EINT_1P8V);
/* set i2c related gpio */
i2c_set_gpio_pinmux();
setup_chromeos_gpios();
if (board_id() < 4)
mt6391_enable_reset_when_ap_resets();
}
asmlinkage void *romstage_main(FSP_INFO_HEADER *fih)
{
void *top_of_stack;
struct pei_data pei_data;
struct romstage_params params = {
.pei_data = &pei_data,
.chipset_context = fih,
};
post_code(0x30);
timestamp_add_now(TS_START_ROMSTAGE);
/* Load microcode before RAM init */
if (IS_ENABLED(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS))
intel_update_microcode_from_cbfs();
memset(&pei_data, 0, sizeof(pei_data));
/* Display parameters */
printk(BIOS_SPEW, "CONFIG_MMCONF_BASE_ADDRESS: 0x%08x\n",
CONFIG_MMCONF_BASE_ADDRESS);
printk(BIOS_INFO, "Using FSP 1.1\n");
/* Display FSP banner */
print_fsp_info(fih);
/* Stash FSP version. */
params.fsp_version = fsp_version(fih);
/* Get power state */
params.power_state = fill_power_state();
/*
* Read and print board version. Done after SOC romstage
* in case PCH needs to be configured to talk to the EC.
*/
if (IS_ENABLED(CONFIG_BOARD_ID_AUTO))
printk(BIOS_INFO, "MLB: board version %d\n", board_id());
/* Call into mainboard. */
mainboard_romstage_entry(¶ms);
soc_after_ram_init(¶ms);
post_code(0x38);
top_of_stack = setup_stack_and_mtrrs();
printk(BIOS_DEBUG, "Calling FspTempRamExit API\n");
timestamp_add_now(TS_FSP_TEMP_RAM_EXIT_START);
return top_of_stack;
}
static void mainboard_init(void *chip_info)
{
int boardid;
const struct pad_config *pads;
size_t num;
boardid = board_id();
printk(BIOS_INFO, "Board ID: %d\n", boardid);
pads = variant_gpio_table(&num);
gpio_configure_pads(pads, num);
mainboard_ec_init();
}
const struct rk3288_sdram_params *get_sdram_config()
{
u32 ramcode;
/* early boards had incorrect config */
if (board_id() == 0)
return &sdram_configs[0];
ramcode = ram_code();
if (ramcode >= ARRAY_SIZE(sdram_configs)
|| sdram_configs[ramcode].dramtype == UNUSED)
die("Invalid RAMCODE.");
return &sdram_configs[ramcode];
}
static int get_wp_status_gpio_pin(void)
{
uint8_t board_rev = board_id();
switch (board_rev) {
case BOARD_ID_GALE_PROTO:
case BOARD_ID_GALE_EVT:
case BOARD_ID_GALE_EVT2_0:
case BOARD_ID_GALE_EVT2_1:
return 6;
case BOARD_ID_GALE_EVT3:
default:
return 53;
}
}
void bootblock_mainboard_init(void)
{
/* adjust gpio params when external voltage is 1.8V */
gpio_init(GPIO_EINT_1P8V);
/* set i2c related gpio */
i2c_set_gpio_pinmux();
mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD1_MASK, 6*MHz);
setup_chromeos_gpios();
if (board_id() < 4)
mt6391_enable_reset_when_ap_resets();
}
static void configure_hdmi(void)
{
rk808_configure_switch(2, 1); /* VCC18_LCD (HDMI_AVDD_1V8) */
rk808_configure_ldo(7, 1000); /* VDD10_LCD (HDMI_AVDD_1V0) */
/* set POWER_HDMI_EN */
switch (board_id()) {
case 0:
gpio_output(GPIO(7, A, 2), 1);
break;
default:
gpio_output(GPIO(5, C, 3), 1);
break;
}
}
static void lb_board_id(struct lb_header *header)
{
struct lb_strapping_id *rec;
uint32_t bid = board_id();
if (bid == UNDEFINED_STRAPPING_ID)
return;
rec = (struct lb_strapping_id *)lb_new_record(header);
rec->tag = LB_TAG_BOARD_ID;
rec->size = sizeof(*rec);
rec->id_code = bid;
printk(BIOS_INFO, "Board ID: %d\n", bid);
}
void board_nand_init(void)
{
struct ebi2cr_regs *ebi2_regs;
if (board_id() != BOARD_ID_PROTO_0_2_NAND)
return;
ebi2_regs = (struct ebi2cr_regs *) EBI2CR_BASE;
nand_clock_config();
configure_nand_gpio();
/* NAND Flash is connected to CS0 */
clrsetbits_le32(&ebi2_regs->chip_select_cfg0, CS0_CFG_MASK,
CS0_CFG_SERIAL_FLASH_DEVICE);
}
static void configure_usb(void)
{
gpio_output(GPIO(0, B, 3), 1); /* HOST1_PWR_EN */
gpio_output(GPIO(0, B, 4), 1); /* USBOTG_PWREN_H */
switch (board_id()) {
case 0:
gpio_output(GPIO(7, B, 3), 1); /* 5V_DRV */
break;
case 1:
break; /* 5V_DRV moved to EC in rev2 */
default:
gpio_output(GPIO(7, C, 5), 1); /* 5V_DRV, again */
break;
}
}
static enum dram_speeds get_sdram_index(void)
{
uint32_t id;
id = board_id();
if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN))
switch (id) {
case 4:
return dram_800MHz;
default:
return dram_933MHz;
}
if (IS_ENABLED(CONFIG_BOARD_GOOGLE_GRU))
return dram_800MHz;
}
void mainboard_power_on_backlight(void)
{
switch (board_id()) {
case 0:
gpio_output(GPIO_BACKLIGHT, 0); /* BL_EN */
gpio_output(GPIO(7, A, 2), 1); /* LCD_BL */
mdelay(10);
gpio_output(GPIO_BACKLIGHT, 1); /* BL_EN */
break;
default:
gpio_output(GPIO(2, B, 4), 1); /* BL_PWR_EN */
mdelay(20);
gpio_output(GPIO_BACKLIGHT, 1); /* LCD_BL */
mdelay(10);
gpio_output(GPIO(7, A, 2), 1); /* BL_EN */
break;
}
}
