/* * pci_pre_init * * This routine is called just prior to registering the hose and gives * the board the opportunity to check things. Returning a value of zero * indicates that things are bad & PCI initialization should be aborted. * * Different boards may wish to customize the pci controller structure * (add regions, override default access routines, etc) or perform * certain pre-initialization actions. * */ int pci_pre_init(struct pci_controller *hose) { unsigned long addr; if (!board_with_pci()) { return 0; } /* * Set priority for all PLB3 devices to 0. * Set PLB3 arbiter to fair mode. */ mfsdr(SD0_AMP1, addr); mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00); addr = mfdcr(PLB3_ACR); mtdcr(PLB3_ACR, addr | 0x80000000); /* Sequoia */ /* * Set priority for all PLB4 devices to 0. */ mfsdr(SD0_AMP0, addr); mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00); addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */ mtdcr(PLB4_ACR, addr); /* Sequoia */ /* * As of errata version 0.4, CHIP_8: Incorrect Write to DDR SDRAM. * Workaround: Disable write pipelining to DDR SDRAM by setting * PLB0_ACR[WRP] = 0. */ mtdcr(PLB0_ACR, 0); /* PATCH HAB: WRITE PIPELINING OFF */ /* Segment1 */ mtdcr(PLB1_ACR, 0); /* PATCH HAB: WRITE PIPELINING OFF */ return board_with_pci(); }
/* * Override weak default pci_master_init() */ void pci_master_init(struct pci_controller *hose) { if (!board_with_pci()) return; __pci_master_init(hose); }
/* * pci_target_init * * The bootstrap configuration provides default settings for the pci * inbound map (PIM). But the bootstrap config choices are limited and * may not be sufficient for a given board. * */ void pci_target_init(struct pci_controller *hose) { if (!board_with_pci()) { return; } /* * Set up Direct MMIO registers * * PowerPC440EPX PCI Master configuration. * Map one 1Gig range of PLB/processor addresses to PCI memory space. * PLB address 0xA0000000-0xDFFFFFFF ==> PCI address * 0xA0000000-0xDFFFFFFF * Use byte reversed out routines to handle endianess. * Make this region non-prefetchable. */ /* PMM0 Mask/Attribute - disabled b4 setting */ out32r(PCIX0_PMM0MA, 0x00000000); out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */ /* PMM0 PCI Low Address */ out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ /* 512M + No prefetching, and enable region */ out32r(PCIX0_PMM0MA, 0xE0000001); /* PMM0 Mask/Attribute - disabled b4 setting */ out32r(PCIX0_PMM1MA, 0x00000000); out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */ /* PMM0 PCI Low Address */ out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ /* 512M + No prefetching, and enable region */ out32r(PCIX0_PMM1MA, 0xE0000001); out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */ out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */ out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */ /* * Set up Configuration registers */ /* Program the board's subsystem id/vendor id */ pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, CFG_PCI_SUBSYS_VENDORID); pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID); /* Configure command register as bus master */ pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); /* 240nS PCI clock */ pci_write_config_word(0, PCI_LATENCY_TIMER, 1); /* No error reporting */ pci_write_config_word(0, PCI_ERREN, 0); pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); }
/* * pci_master_init * */ void pci_master_init(struct pci_controller *hose) { unsigned short temp_short; if (!board_with_pci()) { return; } /*--------------------------------------------------------------- * Write the PowerPC440 EP PCI Configuration regs. * Enable PowerPC440 EP to be a master on the PCI bus (PMM). * Enable PowerPC440 EP to act as a PCI memory target (PTM). *--------------------------------------------------------------*/ pci_read_config_word(0, PCI_COMMAND, &temp_short); pci_write_config_word(0, PCI_COMMAND, temp_short | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); }