static void intel_batchbuffer_reset(struct brw_context *brw) { if (brw->batch.last_bo != NULL) { drm_intel_bo_unreference(brw->batch.last_bo); brw->batch.last_bo = NULL; } brw->batch.last_bo = brw->batch.bo; brw_render_cache_set_clear(brw); brw->batch.bo = drm_intel_bo_alloc(brw->bufmgr, "batchbuffer", BATCH_SZ, 4096); if (brw->has_llc) { drm_intel_bo_map(brw->batch.bo, true); brw->batch.map = brw->batch.bo->virtual; }
/* Emit a pipelined flush to either flush render and texture cache for * reading from a FBO-drawn texture, or flush so that frontbuffer * render appears on the screen in DRI1. * * This is also used for the always_flush_cache driconf debug option. */ void brw_emit_mi_flush(struct brw_context *brw) { if (brw->batch.ring == BLT_RING && brw->gen >= 6) { BEGIN_BATCH_BLT(4); OUT_BATCH(MI_FLUSH_DW); OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); ADVANCE_BATCH(); } else { int flags = PIPE_CONTROL_NO_WRITE | PIPE_CONTROL_RENDER_TARGET_FLUSH; if (brw->gen >= 6) { if (brw->gen == 9) { /* Hardware workaround: SKL * * Emit Pipe Control with all bits set to zero before emitting * a Pipe Control with VF Cache Invalidate set. */ brw_emit_pipe_control_flush(brw, 0); } flags |= PIPE_CONTROL_INSTRUCTION_INVALIDATE | PIPE_CONTROL_DEPTH_CACHE_FLUSH | PIPE_CONTROL_VF_CACHE_INVALIDATE | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | PIPE_CONTROL_CS_STALL; if (brw->gen == 6) { /* Hardware workaround: SNB B-Spec says: * * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache * Flush Enable =1, a PIPE_CONTROL with any non-zero * post-sync-op is required. */ brw_emit_post_sync_nonzero_flush(brw); } } brw_emit_pipe_control_flush(brw, flags); } brw_render_cache_set_clear(brw); }