示例#1
0
void test_set_single_bit() {
	bitset bs;
	bs_init(&bs, 2, g_heap);
	bs_set_range(&bs, 0, 1);
	*(bs.m_bc) = 10;
	bs_set(&bs, 63);
	assert_equal(11, *(bs.m_bc));
	bs_set(&bs, 1);
	assert_equal(4611686018427387915, *(bs.m_bc));
	bs_clear(&bs, 1);
	assert_equal(11, *(bs.m_bc));
	bs_clear(&bs, 63);
	assert_equal(10, *(bs.m_bc));
}
示例#2
0
static void mdp4_dtv_encoder_disable(struct drm_encoder *encoder)
{
	struct mdp4_dtv_encoder *mdp4_dtv_encoder = to_mdp4_dtv_encoder(encoder);
	struct mdp4_kms *mdp4_kms = get_kms(encoder);

	if (WARN_ON(!mdp4_dtv_encoder->enabled))
		return;

	mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 0);

	/*
	 * Wait for a vsync so we know the ENABLE=0 latched before
	 * the (connector) source of the vsync's gets disabled,
	 * otherwise we end up in a funny state if we re-enable
	 * before the disable latches, which results that some of
	 * the settings changes for the new modeset (like new
	 * scanout buffer) don't latch properly..
	 */
	mdp_irq_wait(&mdp4_kms->base, MDP4_IRQ_EXTERNAL_VSYNC);

	clk_disable_unprepare(mdp4_dtv_encoder->src_clk);
	clk_disable_unprepare(mdp4_dtv_encoder->hdmi_clk);
	clk_disable_unprepare(mdp4_dtv_encoder->mdp_clk);

	bs_set(mdp4_dtv_encoder, 0);

	mdp4_dtv_encoder->enabled = false;
}
示例#3
0
void free_session_slot(struct session_slot_table *sst, int slotid,
		       uint32_t server_highest, uint32_t target_highest,
		       bool sent)
{
	pthread_mutex_lock(&sst->mutex);
	assert(!bs_get(sst->free_slots, slotid));
	bs_set(sst->free_slots, slotid);
	if (slotid + 1 == sst->highest_used_slotid_plus1) {
		int s = slotid - 1;
		while (s >= 0 && bs_get(sst->free_slots, s))
			--s;
		sst->highest_used_slotid_plus1 = s + 1;
	}
	if (sent) {
		assert(server_highest + 1 >= sst->highest_used_slotid_plus1);
		sst->server_highest_slotid = server_highest;
		sst->target_highest_slotid = target_highest;
		/* increment sequenceid */
		atomic_inc_uint32_t(sst->slots + slotid);
	}
	if (slotid <= target_highest) {
		pthread_cond_signal(&sst->slot_cv);
	}
	pthread_mutex_unlock(&sst->mutex);
}
示例#4
0
void test_next_one() {
	bitset bs;
	bs_init(&bs, 2, g_heap);
	bs_set_range(&bs, 0, 1);
	// test normal usage
	size_t next_pos = bs_next_one(&bs, 0);
	assert_equal(0, next_pos);
	bs_set_range(&bs, 63, 64);
	next_pos = bs_next_one(&bs, 62);
	assert_equal(63, next_pos);
	next_pos = bs_next_one(&bs, 63);
	assert_equal(63, next_pos);

	// test when there is no one
	bs_clear_range(&bs, 0, 127);
	assert_equal(0x0, bs.m_bc[0]);
	assert_equal(0x0, bs.m_bc[1]);

	next_pos = bs_next_one(&bs, 0);
	assert_equal(next_pos, BITSET_NON);

	// test starts from second chunk
	bs_set_range(&bs, 66, 69);
	next_pos = bs_next_one(&bs, 65);
	assert_equal(66, next_pos);

	// test start point off zero
	bs_clear_range(&bs, 66, 69);
	bs_set(&bs, 0);
	next_pos = bs_next_one(&bs, 0);
	assert_equal(0, next_pos);
	next_pos = bs_next_one(&bs, 1);// off by 1
	assert_equal(BITSET_NON, next_pos);
}
示例#5
0
文件: segmenter.c 项目: ermakus/stm
void
seg_markFile( btFileSet *fs, char *filename, kBitSet *interest) {
    btFile *f;
    int ifile;
    int i;

    /* not interested in anything yet */
    for (i = 0; i<interest->nbits; i++) {
	bs_clr( interest, i);
    }

    /* find the file to be downloaded, and mark interest in it */
    for (ifile = 0; ifile < fs->nfiles; ifile++) {
        int startblock, endblock;

	f = fs->file[ifile];
	startblock = (int)(f->start / (_int64)fs->blocksize);
	endblock = (int)((f->start + f->len - 1) / (_int64)fs->blocksize) + 1;

        if (strstr(f->path, filename)!=NULL) {
	    int i;
	    for (i=startblock; i<endblock; i++) {
		bs_set( interest, i);
	    }
	}
    } 
}
static int enable_axi(struct msm_gpu *gpu)
{
	if (gpu->ebi1_clk)
		clk_prepare_enable(gpu->ebi1_clk);
	if (gpu->bus_freq)
		bs_set(gpu, gpu->bus_freq);
	return 0;
}
static int disable_axi(struct msm_gpu *gpu)
{
	if (gpu->ebi1_clk)
		clk_disable_unprepare(gpu->ebi1_clk);
	if (gpu->bus_freq)
		bs_set(gpu, 0);
	return 0;
}
示例#8
0
static void mdp4_lcdc_encoder_enable(struct drm_encoder *encoder)
{
	struct drm_device *dev = encoder->dev;
	struct mdp4_lcdc_encoder *mdp4_lcdc_encoder =
			to_mdp4_lcdc_encoder(encoder);
	unsigned long pc = mdp4_lcdc_encoder->pixclock;
	struct mdp4_kms *mdp4_kms = get_kms(encoder);
	struct drm_panel *panel;
	uint32_t config;
	int i, ret;

	if (WARN_ON(mdp4_lcdc_encoder->enabled))
		return;

	/* TODO: hard-coded for 18bpp: */
	config =
		MDP4_DMA_CONFIG_R_BPC(BPC6) |
		MDP4_DMA_CONFIG_G_BPC(BPC6) |
		MDP4_DMA_CONFIG_B_BPC(BPC6) |
		MDP4_DMA_CONFIG_PACK(0x21) |
		MDP4_DMA_CONFIG_DEFLKR_EN |
		MDP4_DMA_CONFIG_DITHER_EN;

	if (!of_property_read_bool(dev->dev->of_node, "qcom,lcdc-align-lsb"))
		config |= MDP4_DMA_CONFIG_PACK_ALIGN_MSB;

	mdp4_crtc_set_config(encoder->crtc, config);
	mdp4_crtc_set_intf(encoder->crtc, INTF_LCDC_DTV, 0);

	bs_set(mdp4_lcdc_encoder, 1);

	for (i = 0; i < ARRAY_SIZE(mdp4_lcdc_encoder->regs); i++) {
		ret = regulator_enable(mdp4_lcdc_encoder->regs[i]);
		if (ret)
			DRM_DEV_ERROR(dev->dev, "failed to enable regulator: %d\n", ret);
	}

	DBG("setting lcdc_clk=%lu", pc);
	ret = clk_set_rate(mdp4_lcdc_encoder->lcdc_clk, pc);
	if (ret)
		DRM_DEV_ERROR(dev->dev, "failed to configure lcdc_clk: %d\n", ret);
	ret = clk_prepare_enable(mdp4_lcdc_encoder->lcdc_clk);
	if (ret)
		DRM_DEV_ERROR(dev->dev, "failed to enable lcdc_clk: %d\n", ret);

	panel = of_drm_find_panel(mdp4_lcdc_encoder->panel_node);
	if (!IS_ERR(panel)) {
		drm_panel_prepare(panel);
		drm_panel_enable(panel);
	}

	setup_phy(encoder);

	mdp4_write(mdp4_kms, REG_MDP4_LCDC_ENABLE, 1);

	mdp4_lcdc_encoder->enabled = true;
}
示例#9
0
static void mdp5_encoder_dpms(struct drm_encoder *encoder, int mode)
{
	struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
	struct mdp5_kms *mdp5_kms = get_kms(encoder);
	int intf = mdp5_encoder->intf;
	bool enabled = (mode == DRM_MODE_DPMS_ON);

	DBG("mode=%d", mode);

	if (enabled == mdp5_encoder->enabled)
		return;

	if (enabled) {
		bs_set(mdp5_encoder, 1);
		mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(intf), 1);
	} else {
		mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(intf), 0);
		bs_set(mdp5_encoder, 0);
	}

	mdp5_encoder->enabled = enabled;
}
static void mdp4_lcdc_encoder_enable(struct drm_encoder *encoder)
{
	struct drm_device *dev = encoder->dev;
	struct mdp4_lcdc_encoder *mdp4_lcdc_encoder =
			to_mdp4_lcdc_encoder(encoder);
	unsigned long pc = mdp4_lcdc_encoder->pixclock;
	struct mdp4_kms *mdp4_kms = get_kms(encoder);
	struct drm_panel *panel = mdp4_lcdc_encoder->panel;
	int i, ret;

	if (WARN_ON(mdp4_lcdc_encoder->enabled))
		return;

	/* TODO: hard-coded for 18bpp: */
	mdp4_crtc_set_config(encoder->crtc,
			MDP4_DMA_CONFIG_R_BPC(BPC6) |
			MDP4_DMA_CONFIG_G_BPC(BPC6) |
			MDP4_DMA_CONFIG_B_BPC(BPC6) |
			MDP4_DMA_CONFIG_PACK_ALIGN_MSB |
			MDP4_DMA_CONFIG_PACK(0x21) |
			MDP4_DMA_CONFIG_DEFLKR_EN |
			MDP4_DMA_CONFIG_DITHER_EN);
	mdp4_crtc_set_intf(encoder->crtc, INTF_LCDC_DTV, 0);

	bs_set(mdp4_lcdc_encoder, 1);

	for (i = 0; i < ARRAY_SIZE(mdp4_lcdc_encoder->regs); i++) {
		ret = regulator_enable(mdp4_lcdc_encoder->regs[i]);
		if (ret)
			dev_err(dev->dev, "failed to enable regulator: %d\n", ret);
	}

	DBG("setting lcdc_clk=%lu", pc);
	ret = clk_set_rate(mdp4_lcdc_encoder->lcdc_clk, pc);
	if (ret)
		dev_err(dev->dev, "failed to configure lcdc_clk: %d\n", ret);
	ret = clk_prepare_enable(mdp4_lcdc_encoder->lcdc_clk);
	if (ret)
		dev_err(dev->dev, "failed to enable lcdc_clk: %d\n", ret);

	if (panel) {
		drm_panel_prepare(panel);
		drm_panel_enable(panel);
	}

	setup_phy(encoder);

	mdp4_write(mdp4_kms, REG_MDP4_LCDC_ENABLE, 1);

	mdp4_lcdc_encoder->enabled = true;
}
static void mdp5_cmd_encoder_disable(struct drm_encoder *encoder)
{
	struct mdp5_cmd_encoder *mdp5_cmd_enc = to_mdp5_cmd_encoder(encoder);
	struct mdp5_ctl *ctl = mdp5_cmd_enc->ctl;
	struct mdp5_interface *intf = &mdp5_cmd_enc->intf;

	if (WARN_ON(!mdp5_cmd_enc->enabled))
		return;

	pingpong_tearcheck_disable(encoder);

	mdp5_ctl_set_encoder_state(ctl, false);
	mdp5_ctl_commit(ctl, mdp_ctl_flush_mask_encoder(intf));

	bs_set(mdp5_cmd_enc, 0);

	mdp5_cmd_enc->enabled = false;
}
示例#12
0
文件: segmenter.c 项目: ermakus/stm
int seg_review( btFileSet *fs, kBitSet *writeCache, int piece) {
    char *buf;
    int rs = 0;
    int len = seg_piecelen( fs, piece);
    buf = btmalloc(len);
    /* Trick readbuf into reading the block */
    bs_set(writeCache, piece);
    if (seg_readbuf(fs, writeCache, piece, 0, buf, len)) {
        rs = -1;
    } else if (_checkhash( fs, piece, buf)) {
	rs = 1;
    }
    if(rs!=1) {
         bs_clr(writeCache, piece);
    }
    btfree(buf);
    return rs;
}
示例#13
0
static void mdp5_cmd_encoder_enable(struct drm_encoder *encoder)
{
	struct mdp5_cmd_encoder *mdp5_cmd_enc = to_mdp5_cmd_encoder(encoder);
	struct mdp5_ctl *ctl = mdp5_crtc_get_ctl(encoder->crtc);
	struct mdp5_interface *intf = &mdp5_cmd_enc->intf;

	if (WARN_ON(mdp5_cmd_enc->enabled))
		return;

	bs_set(mdp5_cmd_enc, 1);
	if (pingpong_tearcheck_enable(encoder))
		return;

	mdp5_ctl_commit(ctl, mdp_ctl_flush_mask_encoder(intf));

	mdp5_ctl_set_encoder_state(ctl, true);

	mdp5_cmd_enc->enabled = true;
}
示例#14
0
void mdp5_cmd_encoder_disable(struct drm_encoder *encoder)
{
	struct mdp5_encoder *mdp5_cmd_enc = to_mdp5_encoder(encoder);
	struct mdp5_ctl *ctl = mdp5_cmd_enc->ctl;
	struct mdp5_interface *intf = mdp5_cmd_enc->intf;
	struct mdp5_pipeline *pipeline = mdp5_crtc_get_pipeline(encoder->crtc);

	if (WARN_ON(!mdp5_cmd_enc->enabled))
		return;

	pingpong_tearcheck_disable(encoder);

	mdp5_ctl_set_encoder_state(ctl, pipeline, false);
	mdp5_ctl_commit(ctl, pipeline, mdp_ctl_flush_mask_encoder(intf), true);

	bs_set(mdp5_cmd_enc, 0);

	mdp5_cmd_enc->enabled = false;
}
示例#15
0
static void mdp4_lcdc_encoder_disable(struct drm_encoder *encoder)
{
	struct drm_device *dev = encoder->dev;
	struct mdp4_lcdc_encoder *mdp4_lcdc_encoder =
			to_mdp4_lcdc_encoder(encoder);
	struct mdp4_kms *mdp4_kms = get_kms(encoder);
	struct drm_panel *panel;
	int i, ret;

	if (WARN_ON(!mdp4_lcdc_encoder->enabled))
		return;

	mdp4_write(mdp4_kms, REG_MDP4_LCDC_ENABLE, 0);

	panel = of_drm_find_panel(mdp4_lcdc_encoder->panel_node);
	if (!IS_ERR(panel)) {
		drm_panel_disable(panel);
		drm_panel_unprepare(panel);
	}

	/*
	 * Wait for a vsync so we know the ENABLE=0 latched before
	 * the (connector) source of the vsync's gets disabled,
	 * otherwise we end up in a funny state if we re-enable
	 * before the disable latches, which results that some of
	 * the settings changes for the new modeset (like new
	 * scanout buffer) don't latch properly..
	 */
	mdp_irq_wait(&mdp4_kms->base, MDP4_IRQ_PRIMARY_VSYNC);

	clk_disable_unprepare(mdp4_lcdc_encoder->lcdc_clk);

	for (i = 0; i < ARRAY_SIZE(mdp4_lcdc_encoder->regs); i++) {
		ret = regulator_disable(mdp4_lcdc_encoder->regs[i]);
		if (ret)
			DRM_DEV_ERROR(dev->dev, "failed to disable regulator: %d\n", ret);
	}

	bs_set(mdp4_lcdc_encoder, 0);

	mdp4_lcdc_encoder->enabled = false;
}
示例#16
0
static void mdp5_cmd_encoder_disable(struct drm_encoder *encoder)
{
	struct mdp5_cmd_encoder *mdp5_cmd_enc = to_mdp5_cmd_encoder(encoder);
	struct mdp5_kms *mdp5_kms = get_kms(encoder);
	struct mdp5_ctl *ctl = mdp5_crtc_get_ctl(encoder->crtc);
	struct mdp5_interface *intf = &mdp5_cmd_enc->intf;
	int lm = mdp5_crtc_get_lm(encoder->crtc);

	if (WARN_ON(!mdp5_cmd_enc->enabled))
		return;

	/* Wait for the last frame done */
	mdp_irq_wait(&mdp5_kms->base, lm2ppdone(lm));
	pingpong_tearcheck_disable(encoder);

	mdp5_ctl_set_encoder_state(ctl, false);
	mdp5_ctl_commit(ctl, mdp_ctl_flush_mask_encoder(intf));

	bs_set(mdp5_cmd_enc, 0);

	mdp5_cmd_enc->enabled = false;
}
示例#17
0
文件: segmenter.c 项目: ermakus/stm
static int
seg_write( btFileSet *fs, btPartialPiece *piece) {
    btFile *f;
    _int64 addr = (_int64)piece->piecenumber * fs->blocksize;
    int ifile;
    for (ifile=0; ifile < fs->nfiles; ifile++) {
	int blocklen = seg_piecelen( fs, piece->piecenumber);
	f=fs->file[ifile];
	if ( f->start+f->len >= addr &&
		f->start < addr + blocklen) 
	{
	    /* this file (partly) includes this piece */
	    _int64 beg = f->start - addr;	
	    off_t fpos=0;
	    _int64 len;
	    int fd = openPath( f->path, O_CREAT | O_WRONLY);
	    if (fd < 0) {
		return -1;
	    }
	    if (beg<0) {
		fpos=-beg;
		beg=0;
	    }
	    len = min(f->len - fpos, (_int64)blocklen - beg);

	    if (lseek( fd, fpos, SEEK_SET) != fpos) {
		return -1;
	    }

	    bt_assert( len <= fs->blocksize);
	    if (write( fd, piece->buffer+beg, len) != len) {
		return -1;
	    }
	}
    }
    bs_set( &fs->completed, piece->piecenumber);
    return 0;
}
示例#18
0
static void mdp4_dtv_encoder_enable(struct drm_encoder *encoder)
{
	struct drm_device *dev = encoder->dev;
	struct mdp4_dtv_encoder *mdp4_dtv_encoder = to_mdp4_dtv_encoder(encoder);
	struct mdp4_kms *mdp4_kms = get_kms(encoder);
	unsigned long pc = mdp4_dtv_encoder->pixclock;
	int ret;

	if (WARN_ON(mdp4_dtv_encoder->enabled))
		return;

	mdp4_crtc_set_config(encoder->crtc,
			MDP4_DMA_CONFIG_R_BPC(BPC8) |
			MDP4_DMA_CONFIG_G_BPC(BPC8) |
			MDP4_DMA_CONFIG_B_BPC(BPC8) |
			MDP4_DMA_CONFIG_PACK(0x21));
	mdp4_crtc_set_intf(encoder->crtc, INTF_LCDC_DTV, 1);

	bs_set(mdp4_dtv_encoder, 1);

	DBG("setting src_clk=%lu", pc);

	ret = clk_set_rate(mdp4_dtv_encoder->src_clk, pc);
	if (ret)
		dev_err(dev->dev, "failed to set src_clk to %lu: %d\n", pc, ret);
	clk_prepare_enable(mdp4_dtv_encoder->src_clk);
	ret = clk_prepare_enable(mdp4_dtv_encoder->hdmi_clk);
	if (ret)
		dev_err(dev->dev, "failed to enable hdmi_clk: %d\n", ret);
	ret = clk_prepare_enable(mdp4_dtv_encoder->mdp_clk);
	if (ret)
		dev_err(dev->dev, "failed to enabled mdp_clk: %d\n", ret);

	mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 1);

	mdp4_dtv_encoder->enabled = true;
}