AFTER_VECTORS void ResetISR(void) { unsigned int LoadAddr, ExeAddr, SectionLen; unsigned int *SectionTableAddr; SectionTableAddr = &__data_section_table; while (SectionTableAddr < &__data_section_table_end) { LoadAddr = *SectionTableAddr++; ExeAddr = *SectionTableAddr++; SectionLen = *SectionTableAddr++; data_init(LoadAddr, ExeAddr, SectionLen); } while (SectionTableAddr < &__bss_section_table_end) { ExeAddr = *SectionTableAddr++; SectionLen = *SectionTableAddr++; bss_init(ExeAddr, SectionLen); } SystemInit(); if (pre_main) { // give control to the RTOS software_init_hook(); // this will also call __libc_init_array } else { // for BareMetal (non-RTOS) build __libc_init_array(); main(); } while (1) {;} }
/* Pintos main program. */ int main (void) { char **argv; /* Clear BSS. */ bss_init (); /* Break command line into arguments and parse options. */ argv = read_command_line (); argv = parse_options (argv); /* Initialize ourselves as a thread so we can use locks, then enable console locking. */ thread_init (); console_init (); /* Greet user. */ printf ("Pintos booting with %'"PRIu32" kB RAM...\n", init_ram_pages * PGSIZE / 1024); /* Initialize memory system. */ palloc_init (user_page_limit); malloc_init (); paging_init (); <<<<<<< HEAD
Reset_Handler(void) { // Use Old Style Data and BSS section initialisation, // That will initialise a single BSS sections. // Zero fill the bss segment bss_init(&__bss_start__, &__bss_end__); // Call the standard library initialisation (mandatory, SystemInit() // and C++ static constructors are called from here). __libc_init_array(); // Call the main entry point, and save the exit code. int r = main(); // Run the static destructors. __libc_fini_array(); // On test platforms, like semi-hosting, this can be used to inform // the host on the test result. // On embedded platforms, usually reset the processor. _exit(r); }
AFTER_VECTORS void ResetISR(void) { unsigned int LoadAddr, ExeAddr, SectionLen; unsigned int *SectionTableAddr; // Data Init SectionTableAddr = &__data_section_table; while (SectionTableAddr < &__data_section_table_end) { LoadAddr = *SectionTableAddr++; ExeAddr = *SectionTableAddr++; SectionLen = *SectionTableAddr++; data_init(LoadAddr, ExeAddr, SectionLen); } // BSS Init while (SectionTableAddr < &__bss_section_table_end) { ExeAddr = *SectionTableAddr++; SectionLen = *SectionTableAddr++; bss_init(ExeAddr, SectionLen); } SystemInit(); if (software_init_hook) // give control to the RTOS software_init_hook(); // this will also call __libc_init_array else { __libc_init_array(); main(); } while (1) {;} }
AFTER_VECTORS void ResetISR(void) { unsigned int LoadAddr, ExeAddr, SectionLen; unsigned int *SectionTableAddr; SectionTableAddr = &__data_section_table; while (SectionTableAddr < &__data_section_table_end) { LoadAddr = *SectionTableAddr++; ExeAddr = *SectionTableAddr++; SectionLen = *SectionTableAddr++; data_init(LoadAddr, ExeAddr, SectionLen); } while (SectionTableAddr < &__bss_section_table_end) { ExeAddr = *SectionTableAddr++; SectionLen = *SectionTableAddr++; bss_init(ExeAddr, SectionLen); } SystemInit(); if (software_init_hook) software_init_hook(); else { __libc_init_array(); main(); } while (1) {;} }
static void isr_reset(void) { // remove compiler warning (void)g_pfnVectors; /** * The hyperload bootloader sets the MSP/PSP upon a true reset, which is when the * LPC17xx (Cortex-M3) sets the values of the stack pointer. But since we are * booting after a bootloader, we have to manually setup the stack pointers ourselves. */ do { const uint32_t topOfStack = (uint32_t) &_vStackTop; __set_PSP(topOfStack); __set_MSP(topOfStack); } while(0); do { // Copy data from FLASH to RAM unsigned int LoadAddr, ExeAddr, SectionLen; unsigned int *SectionTableAddr; // Load base address of Global Section Table SectionTableAddr = &__data_section_table; // Copy the data sections from flash to SRAM. while (SectionTableAddr < &__data_section_table_end) { LoadAddr = *SectionTableAddr++; ExeAddr = *SectionTableAddr++; SectionLen = *SectionTableAddr++; data_init(LoadAddr, ExeAddr, SectionLen); } // At this point, SectionTableAddr = &__bss_section_table; // Zero fill the bss segment while (SectionTableAddr < &__bss_section_table_end) { ExeAddr = *SectionTableAddr++; SectionLen = *SectionTableAddr++; bss_init(ExeAddr, SectionLen); } } while (0) ; #if defined (__cplusplus) __libc_init_array(); // Call C++ library initialization #endif do { low_level_init(); // Initialize minimal system, such as Clock & UART high_level_init(); // Initialize high level board specific features main(); // Finally call main() } while(0); // In case main() exits: uart0_init(SYS_CFG_UART0_BPS); u0_dbg_put("main() should never exit on this system\n"); while (1) { ; } }
void operator()(){ // enable RAM banks that may be off by default at reset volatile unsigned int *SYSCON_SYSAHBCLKCTRL = (unsigned int *) 0x40048080; // Ensure that RAM1(26) and USBSRAM(27) bits in SYSAHBCLKCTRL are set *SYSCON_SYSAHBCLKCTRL |= (1 << 26) | (1 <<27); // Copy the data sections from flash to SRAM. unsigned int LoadAddr, ExeAddr, SectionLen; unsigned int *SectionTableAddr; // Load base address of Global Section Table SectionTableAddr = &__data_section_table; // Copy the data sections from flash to SRAM. while (SectionTableAddr < &__data_section_table_end) { LoadAddr = *SectionTableAddr++; ExeAddr = *SectionTableAddr++; SectionLen = *SectionTableAddr++; data_init(LoadAddr, ExeAddr, SectionLen); } // At this point, SectionTableAddr = &__bss_section_table; // Zero fill the bss segment while (SectionTableAddr < &__bss_section_table_end) { ExeAddr = *SectionTableAddr++; SectionLen = *SectionTableAddr++; bss_init(ExeAddr, SectionLen); } }
int sdb_untrim( sdb_table_t *tbl) { if( tbl->bss_ctx) return SDB_EBADSTATE; else { bss_ctx_t *bss = BS_MEM_ALLOC( sizeof( *bss)); if( ! bss) return SDB_EMEM; bss_init( bss, sdb_bss_writer, tbl); bss->supports_chunks = 0; // Stagedb can't currently handle chunked data tbl->bss_ctx = bss; return SDB_EOK; } }
void ResetISR(void) { // // Copy the data sections from flash to SRAM. // unsigned int LoadAddr, ExeAddr, SectionLen; unsigned int *SectionTableAddr; // Load base address of Global Section Table SectionTableAddr = &__data_section_table; // Copy the data sections from flash to SRAM. while (SectionTableAddr < &__data_section_table_end) { LoadAddr = *SectionTableAddr++; ExeAddr = *SectionTableAddr++; SectionLen = *SectionTableAddr++; data_init(LoadAddr, ExeAddr, SectionLen); } // At this point, SectionTableAddr = &__bss_section_table; // Zero fill the bss segment while (SectionTableAddr < &__bss_section_table_end) { ExeAddr = *SectionTableAddr++; SectionLen = *SectionTableAddr++; bss_init(ExeAddr, SectionLen); } #ifdef __USE_CMSIS SystemInit(); #endif #if defined (__cplusplus) // // Call C++ library initialisation // __libc_init_array(); #endif #if defined (__REDLIB__) // Call the Redlib library, which in turn calls main() __main() ; #else main(); #endif // // main() shouldn't return, but if it does, we'll just enter an infinite loop // while (1) { ; } }
void ResetISR(void) { // // Copy the data sections from flash to SRAM. // unsigned int LoadAddr, ExeAddr, SectionLen; unsigned int *SectionTableAddr; // Load base address of Global Section Table SectionTableAddr = &__data_section_table; // Copy the data sections from flash to SRAM. while (SectionTableAddr < &__data_section_table_end) { LoadAddr = *SectionTableAddr++; ExeAddr = *SectionTableAddr++; SectionLen = *SectionTableAddr++; data_init(LoadAddr, ExeAddr, SectionLen); } // At this point, SectionTableAddr = &__bss_section_table; // Zero fill the bss segment while (SectionTableAddr < &__bss_section_table_end) { ExeAddr = *SectionTableAddr++; SectionLen = *SectionTableAddr++; bss_init(ExeAddr, SectionLen); } low_level_init(); main(); // // main() shouldn't return, but if it does, we'll just enter an infinite loop // while (1) ; }
void secure_task(void) { unsigned *pcommand = (unsigned *)(&(secure_task_share_mem[TASK_COMMAND_OFFSET])); unsigned *response = (unsigned *)(&(secure_task_share_mem[TASK_RESPONSE_OFFSET])); unsigned command; struct resume_param *presume; unsigned int state; /*init bss */ bss_init(); dbg_prints("secure task start!\n"); /* suspend pwr ops init*/ suspend_pwr_ops_init(); *pcommand = 0; while (1) { /* do secure task process */ command = *pcommand; if (command) { dbg_print("process command ", command); if (command == SEC_TASK_GET_WAKEUP_SRC) { state = *(pcommand+1); suspend_get_wakeup_source( (void *)response, state); } else if (command == COMMAND_SUSPEND_ENTER) { state = *(pcommand+1); enter_suspend(state); *pcommand = 0; *response = RESPONSE_SUSPEND_LEAVE; presume = (struct resume_param *)(response+1); presume->method = resume_data.method; } } __switch_back_highmb(); } }
void ResetISR(void) { // // Copy the data sections from flash to SRAM. // unsigned int LoadAddr, ExeAddr, SectionLen; unsigned int *SectionTableAddr; // Load base address of Global Section Table SectionTableAddr = &__data_section_table; // Copy the data sections from flash to SRAM. while (SectionTableAddr < &__data_section_table_end) { LoadAddr = *SectionTableAddr++; ExeAddr = *SectionTableAddr++; SectionLen = *SectionTableAddr++; data_init(LoadAddr, ExeAddr, SectionLen); } // At this point, SectionTableAddr = &__bss_section_table; // Zero fill the bss segment while (SectionTableAddr < &__bss_section_table_end) { ExeAddr = *SectionTableAddr++; SectionLen = *SectionTableAddr++; bss_init(ExeAddr, SectionLen); } // Patch the AEABI integer divide functions to use MCU's romdivide library #ifdef __USE_ROMDIVIDE // Get address of Integer division routines function table in ROM unsigned int *div_ptr = (unsigned int *)((unsigned int *)*(PTR_ROM_DRIVER_TABLE))[4]; // Get addresses of integer divide routines in ROM // These address are then used by the code in aeabi_romdiv_patch.s pDivRom_idiv = (unsigned int *)div_ptr[0]; pDivRom_uidiv = (unsigned int *)div_ptr[1]; #endif #if defined (__USE_CMSIS) || defined (__USE_LPCOPEN) SystemInit(); #endif #if defined (__cplusplus) // // Call C++ library initialisation // __libc_init_array(); #endif #if defined (__REDLIB__) // Call the Redlib library, which in turn calls main() __main() ; #else main(); #endif // // main() shouldn't return, but if it does, we'll just enter an infinite loop // while (1) { ; } }
//***************************************************************************** // Reset entry point for your code. // Sets up a simple runtime environment and initializes the C/C++ // library. // //***************************************************************************** void ResetISR(void) { // ************************************************************* // The following conditional block of code manually resets as // much of the peripheral set of the LPC43 as possible. This is // done because the LPC43 does not provide a means of triggering // a full system reset under debugger control, which can cause // problems in certain circumstances when debugging. // // You can prevent this code block being included if you require // (for example when creating a final executable which you will // not debug) by setting the define 'DONT_RESET_ON_RESTART'. // #ifndef DONT_RESET_ON_RESTART // Disable interrupts __asm volatile ("cpsid i"); // equivalent to CMSIS '__disable_irq()' function unsigned int *RESET_CONTROL = (unsigned int *) 0x40053100; // LPC_RGU->RESET_CTRL0 @ 0x40053100 // LPC_RGU->RESET_CTRL1 @ 0x40053104 // Note that we do not use the CMSIS register access mechanism, // as there is no guarantee that the project has been configured // to use CMSIS. // Write to LPC_RGU->RESET_CTRL0 *(RESET_CONTROL + 0) = 0x10DF1000; // GPIO_RST|AES_RST|ETHERNET_RST|SDIO_RST|DMA_RST| // USB1_RST|USB0_RST|LCD_RST|M0_SUB_RST // Write to LPC_RGU->RESET_CTRL1 *(RESET_CONTROL + 1) = 0x01DFF7FF; // M0APP_RST|CAN0_RST|CAN1_RST|I2S_RST|SSP1_RST|SSP0_RST| // I2C1_RST|I2C0_RST|UART3_RST|UART1_RST|UART1_RST|UART0_RST| // DAC_RST|ADC1_RST|ADC0_RST|QEI_RST|MOTOCONPWM_RST|SCT_RST| // RITIMER_RST|TIMER3_RST|TIMER2_RST|TIMER1_RST|TIMER0_RST // Clear all pending interrupts in the NVIC volatile unsigned int *NVIC_ICPR = (unsigned int *) 0xE000E280; unsigned int irqpendloop; for (irqpendloop = 0; irqpendloop < 8; irqpendloop++) { *(NVIC_ICPR + irqpendloop) = 0xFFFFFFFF; } // Reenable interrupts __asm volatile ("cpsie i"); // equivalent to CMSIS '__enable_irq()' function #endif // ifndef DONT_RESET_ON_RESTART // ************************************************************* #if defined (__USE_LPCOPEN) SystemInit(); #endif // // Copy the data sections from flash to SRAM. // unsigned int LoadAddr, ExeAddr, SectionLen; unsigned int *SectionTableAddr; // Load base address of Global Section Table SectionTableAddr = &__data_section_table; // Copy the data sections from flash to SRAM. while (SectionTableAddr < &__data_section_table_end) { LoadAddr = *SectionTableAddr++; ExeAddr = *SectionTableAddr++; SectionLen = *SectionTableAddr++; data_init(LoadAddr, ExeAddr, SectionLen); } // At this point, SectionTableAddr = &__bss_section_table; // Zero fill the bss segment while (SectionTableAddr < &__bss_section_table_end) { ExeAddr = *SectionTableAddr++; SectionLen = *SectionTableAddr++; bss_init(ExeAddr, SectionLen); } #if !defined (__USE_LPCOPEN) // LPCOpen init code deals with FP and VTOR initialisation #if defined (__VFP_FP__) && !defined (__SOFTFP__) /* * Code to enable the Cortex-M4 FPU only included * if appropriate build options have been selected. * Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C) */ // CPACR is located at address 0xE000ED88 asm("LDR.W R0, =0xE000ED88"); // Read CPACR asm("LDR R1, [R0]"); // Set bits 20-23 to enable CP10 and CP11 coprocessors asm(" ORR R1, R1, #(0xF << 20)"); // Write back the modified value to the CPACR asm("STR R1, [R0]"); #endif // (__VFP_FP__) && !(__SOFTFP__) // ****************************** // Check to see if we are running the code from a non-zero // address (eg RAM, external flash), in which case we need // to modify the VTOR register to tell the CPU that the // vector table is located at a non-0x0 address. // Note that we do not use the CMSIS register access mechanism, // as there is no guarantee that the project has been configured // to use CMSIS. unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08; if ((unsigned int *) g_pfnVectors != (unsigned int *) 0x00000000) { // CMSIS : SCB->VTOR = <address of vector table> *pSCB_VTOR = (unsigned int) g_pfnVectors; } #endif #if defined (__USE_CMSIS) SystemInit(); #endif #if defined (__cplusplus) // // Call C++ library initialisation // __libc_init_array(); #endif #if defined (__REDLIB__) // Call the Redlib library, which in turn calls main() __main(); #else main(); #endif // // main() shouldn't return, but if it does, we'll just enter an infinite loop // while (1) { ; } }
void ResetISR(void) { // Optionally enable RAM banks that may be off by default at reset #if !defined (DONT_ENABLE_DISABLED_RAMBANKS) volatile unsigned int *SYSCON_SYSAHBCLKCTRL = (unsigned int *) 0x40048080; // Ensure that RAM1(26) and USBSRAM(27) bits in SYSAHBCLKCTRL are set *SYSCON_SYSAHBCLKCTRL |= (1 << 26) | (1 <<27); #endif // // Copy the data sections from flash to SRAM. // unsigned int LoadAddr, ExeAddr, SectionLen; unsigned int *SectionTableAddr; // Load base address of Global Section Table SectionTableAddr = &__data_section_table; // Copy the data sections from flash to SRAM. while (SectionTableAddr < &__data_section_table_end) { LoadAddr = *SectionTableAddr++; ExeAddr = *SectionTableAddr++; SectionLen = *SectionTableAddr++; data_init(LoadAddr, ExeAddr, SectionLen); } // At this point, SectionTableAddr = &__bss_section_table; // Zero fill the bss segment while (SectionTableAddr < &__bss_section_table_end) { ExeAddr = *SectionTableAddr++; SectionLen = *SectionTableAddr++; bss_init(ExeAddr, SectionLen); } // Patch the AEABI integer divide functions to use MCU's romdivide library #ifdef __USE_ROMDIVIDE // Get address of Integer division routines function table in ROM unsigned int *div_ptr = (unsigned int *)((unsigned int *)*(PTR_ROM_DRIVER_TABLE))[4]; // Get addresses of integer divide routines in ROM // These address are then used by the code in aeabi_romdiv_patch.s pDivRom_idiv = (unsigned int *)div_ptr[0]; pDivRom_uidiv = (unsigned int *)div_ptr[1]; #endif #if defined (__USE_CMSIS) || defined (__USE_LPCOPEN) SystemInit(); #endif #if defined (__cplusplus) // // Call C++ library initialisation // __libc_init_array(); #endif #if defined (__REDLIB__) // Call the Redlib library, which in turn calls main() __main() ; #else main(); #endif // // main() shouldn't return, but if it does, we'll just enter an infinite loop // while (1) { ; } }
void ResetISR(void) { // remove warning (void)g_pfnVectors; #ifndef USE_OLD_STYLE_DATA_BSS_INIT // // Copy the data sections from flash to SRAM. // unsigned int LoadAddr, ExeAddr, SectionLen; unsigned int *SectionTableAddr; // Load base address of Global Section Table SectionTableAddr = &__data_section_table; // Copy the data sections from flash to SRAM. while (SectionTableAddr < &__data_section_table_end) { LoadAddr = *SectionTableAddr++; ExeAddr = *SectionTableAddr++; SectionLen = *SectionTableAddr++; data_init(LoadAddr, ExeAddr, SectionLen); } // At this point, SectionTableAddr = &__bss_section_table; // Zero fill the bss segment while (SectionTableAddr < &__bss_section_table_end) { ExeAddr = *SectionTableAddr++; SectionLen = *SectionTableAddr++; bss_init(ExeAddr, SectionLen); } #else // Use Old Style Data and BSS section initialization. // This will only initialize a single RAM bank. unsigned int * LoadAddr, *ExeAddr, *EndAddr, SectionLen; // Copy the data segment from flash to SRAM. LoadAddr = &_etext; ExeAddr = &_data; EndAddr = &_edata; SectionLen = (void*)EndAddr - (void*)ExeAddr; data_init((unsigned int)LoadAddr, (unsigned int)ExeAddr, SectionLen); // Zero fill the bss segment ExeAddr = &_bss; EndAddr = &_ebss; SectionLen = (void*)EndAddr - (void*)ExeAddr; bss_init ((unsigned int)ExeAddr, SectionLen); #endif #if defined (__cplusplus) // // Call C++ library initialization // __libc_init_array(); #endif // Functions defined externally to this file: extern void lowLevelInitialize(void); extern void highLevelInitialize(void); extern int main(); lowLevelInitialize(); // Initialize minimal system, such as Clock & UART highLevelInitialize(); // Initialize any user desired items int exit_code = main(); // Finally call main() // In case main() exits: uart0Init(UART0_DEFAULT_RATE_BPS, (getCpuClock() / 4)); stdio_SetOutputCharFunction(uart0Putchar); stdio_SetInputCharFunction(uart0Getchar); printf("main() exited with return code %i\n", exit_code); printf("main() should never exit on an Embedded System\n"); while (1) ; }
void ResetISR(void) { #ifndef USE_OLD_STYLE_DATA_BSS_INIT // // Copy the data sections from flash to SRAM. // unsigned int LoadAddr, ExeAddr, SectionLen; unsigned int *SectionTableAddr; // Load base address of Global Section Table SectionTableAddr = &__data_section_table; // Copy the data sections from flash to SRAM. while (SectionTableAddr < &__data_section_table_end) { LoadAddr = *SectionTableAddr++; ExeAddr = *SectionTableAddr++; SectionLen = *SectionTableAddr++; data_init(LoadAddr, ExeAddr, SectionLen); } // At this point, SectionTableAddr = &__bss_section_table; // Zero fill the bss segment while (SectionTableAddr < &__bss_section_table_end) { ExeAddr = *SectionTableAddr++; SectionLen = *SectionTableAddr++; bss_init(ExeAddr, SectionLen); } #else // Use Old Style Data and BSS section initialization. // This will only initialize a single RAM bank. unsigned int * LoadAddr, *ExeAddr, *EndAddr, SectionLen; // Copy the data segment from flash to SRAM. LoadAddr = &_etext; ExeAddr = &_data; EndAddr = &_edata; SectionLen = (void*)EndAddr - (void*)ExeAddr; data_init((unsigned int)LoadAddr, (unsigned int)ExeAddr, SectionLen); // Zero fill the bss segment ExeAddr = &_bss; EndAddr = &_ebss; SectionLen = (void*)EndAddr - (void*)ExeAddr; bss_init ((unsigned int)ExeAddr, SectionLen); #endif #if defined (__VFP_FP__) && !defined (__SOFTFP__) /* * Code to enable the Cortex-M4 FPU only included * if appropriate build options have been selected. * Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C) */ // asm(".syntax unified"); // CPACR is located at address 0xE000ED88 asm("LDR.W R0, =0xE000ED88"); // Read CPACR asm("LDR R1, [R0]"); // Set bits 20-23 to enable CP10 and CP11 coprocessors asm(" ORR R1, R1, #(0xF << 20)"); // Write back the modified value to the CPACR asm("STR R1, [R0]"); // asm(".syntax divided"); #endif // (__VFP_FP__) && !(__SOFTFP__) #ifdef __USE_CMSIS SystemInit(); #endif #if defined (__cplusplus) // // Call C++ library initialisation // __libc_init_array(); #endif #if defined (__REDLIB__) // Call the Redlib library, which in turn calls main() __main() ; #else main(); #endif // // main() shouldn't return, but if it does, we'll just enter an infinite loop // while (1) { ; } }
void ResetISR(void) { // // Copy the data sections from flash to SRAM. // unsigned int LoadAddr, ExeAddr, SectionLen; unsigned int *SectionTableAddr; // Load base address of Global Section Table SectionTableAddr = &__data_section_table; // Copy the data sections from flash to SRAM. while (SectionTableAddr < &__data_section_table_end) { LoadAddr = *SectionTableAddr++; ExeAddr = *SectionTableAddr++; SectionLen = *SectionTableAddr++; data_init(LoadAddr, ExeAddr, SectionLen); } // At this point, SectionTableAddr = &__bss_section_table; // Zero fill the bss segment while (SectionTableAddr < &__bss_section_table_end) { ExeAddr = *SectionTableAddr++; SectionLen = *SectionTableAddr++; bss_init(ExeAddr, SectionLen); } // Optionally enable Cortex-M3 SWV trace (off by default at reset) // Note - your board support must also set up the switch matrix // so that SWO is output on the appropriate pin for your hardware #if !defined (DONT_ENABLE_SWVTRACECLK) // Write 0x00000001 to TRACECLKDIV – Trace divider volatile unsigned int *TRACECLKDIV = (unsigned int *) 0x400740D8; *TRACECLKDIV = 1; #endif #if defined (__USE_CMSIS) || defined (__USE_LPCOPEN) SystemInit(); #endif #if defined (__cplusplus) // // Call C++ library initialisation // __libc_init_array(); #endif #if defined (__REDLIB__) // Call the Redlib library, which in turn calls main() __main() ; #else main(); #endif // // main() shouldn't return, but if it does, we'll just enter an infinite loop // while (1) { ; } }
//***************************************************************************** // Reset entry point for your code. // Sets up a simple runtime environment and initializes the C/C++ // library. // //***************************************************************************** void ResetISR(void) { // ****************************** // Modify CREG->M0APPMAP so that M0 looks in correct place // for its vector table when an exception is triggered. // Note that we do not use the CMSIS register access mechanism, // as there is no guarantee that the project has been configured // to use CMSIS. unsigned int *pCREG_M0APPMAP = (unsigned int *) 0x40043404; // CMSIS : CREG->M0APPMAP = <address of vector table> *pCREG_M0APPMAP = (unsigned int)g_pfnVectors; // // Copy the data sections from flash to SRAM. // unsigned int LoadAddr, ExeAddr, SectionLen; unsigned int *SectionTableAddr; // Load base address of Global Section Table SectionTableAddr = &__data_section_table; // Copy the data sections from flash to SRAM. while (SectionTableAddr < &__data_section_table_end) { LoadAddr = *SectionTableAddr++; ExeAddr = *SectionTableAddr++; SectionLen = *SectionTableAddr++; data_init(LoadAddr, ExeAddr, SectionLen); } // At this point, SectionTableAddr = &__bss_section_table; // Zero fill the bss segment while (SectionTableAddr < &__bss_section_table_end) { ExeAddr = *SectionTableAddr++; SectionLen = *SectionTableAddr++; bss_init(ExeAddr, SectionLen); } // ********************************************************** // No need to call SystemInit() here, as master CM4 cpu will // have done the main system set up before enabling CM0. // ********************************************************** #if defined (__cplusplus) // // Call C++ library initialisation // __libc_init_array(); #endif #if defined (__REDLIB__) // Call the Redlib library, which in turn calls main() __main() ; #else main(); #endif // // main() shouldn't return, but if it does, we'll just enter an infinite loop // while (1) { ; } }
void Reset_Handler(void) { // Copy the data sections from flash to SRAM. unsigned int LoadAddr, ExeAddr, SectionLen; unsigned int *SectionTableAddr; // Load base address of Global Section Table SectionTableAddr = &__data_section_table; // Copy the data sections from flash to SRAM. while (SectionTableAddr < &__data_section_table_end) { LoadAddr = *SectionTableAddr++; ExeAddr = *SectionTableAddr++; SectionLen = *SectionTableAddr++; data_init(LoadAddr, ExeAddr, SectionLen); } // At this point, SectionTableAddr = &__bss_section_table; // Zero fill the bss segment while (SectionTableAddr < &__bss_section_table_end) { ExeAddr = *SectionTableAddr++; SectionLen = *SectionTableAddr++; bss_init(ExeAddr, SectionLen); } #if STARTUP_DELAY volatile unsigned int i; for(i=0; i<STARTUP_DELAY; i++); #endif // Set clock mode, DEFAULT_CLOCK is defined in config.h, and the default behaviour // is to set the clock to 72MHz from the external crystal. Using defines here to // reduce code space #if DEFAULT_CLOCK == XTAL ClockModeXTAL(); #elif DEFAULT_CLOCK == IRC72 ClockModeIRC72(); #elif DEFAULT_CLOCK == IRC12 ClockModeIRC12(); #endif LPC_SYSCON->SYSAHBCLKDIV = 1; LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 6) | (1 << 16); // Set all pins to digital inputs (except P0[0] which is the reset button) #if PORT_STARTUP_INIT Port0Init(ALL & ~PIN0); Port1Init(ALL); #endif // Initialise and start the system tick timer if allowed by the SYSTICK_EN // definition in config.h, if the system tick timer is running, then the Delay() // function will use it, otherwise Delay() will use a fixed loop which is not // accurate when there are interrupts running, as any interrupt would stop the // loop and cuase the delay to be longer than expected #if SYSTICK_EN && SYSTICK_STARTUP SysTickInit(); #endif // Run the user-supplied setup() function if it exists if(setup) { setup(); } // Run the user-supplied main() function if it exists if(main) { main(); } // Loop the user-supplied setup() function if it exists if(loop) { while(1) loop(); } // Do nothing (except handle interrupts) while(1); }
void ResetISR(void) { #ifndef USE_OLD_STYLE_DATA_BSS_INIT // // Copy the data sections from flash to SRAM. // unsigned int LoadAddr, ExeAddr, SectionLen; unsigned int *SectionTableAddr; // Load base address of Global Section Table SectionTableAddr = &__data_section_table; // Copy the data sections from flash to SRAM. while (SectionTableAddr < &__data_section_table_end) { LoadAddr = *SectionTableAddr++; ExeAddr = *SectionTableAddr++; SectionLen = *SectionTableAddr++; data_init(LoadAddr, ExeAddr, SectionLen); } // At this point, SectionTableAddr = &__bss_section_table; // Zero fill the bss segment while (SectionTableAddr < &__bss_section_table_end) { ExeAddr = *SectionTableAddr++; SectionLen = *SectionTableAddr++; bss_init(ExeAddr, SectionLen); } #else // Use Old Style Data and BSS section initialization. // This will only initialize a single RAM bank. unsigned int * LoadAddr, *ExeAddr, *EndAddr, SectionLen; // Copy the data segment from flash to SRAM. LoadAddr = &_etext; ExeAddr = &_data; EndAddr = &_edata; SectionLen = (void*)EndAddr - (void*)ExeAddr; data_init((unsigned int)LoadAddr, (unsigned int)ExeAddr, SectionLen); // Zero fill the bss segment ExeAddr = &_bss; EndAddr = &_ebss; SectionLen = (void*)EndAddr - (void*)ExeAddr; bss_init ((unsigned int)ExeAddr, SectionLen); #endif #ifdef __USE_CMSIS SystemInit(); #endif #if defined (__cplusplus) // // Call C++ library initialisation // __libc_init_array(); #endif #if defined (__REDLIB__) // Call the Redlib library, which in turn calls main() __main() ; #else main(); #endif // // main() shouldn't return, but if it does, we'll just enter an infinite loop // while (1) { ; } }
void ResetISR(void) { // // Copy the data sections from flash to SRAM. // unsigned int LoadAddr, ExeAddr, SectionLen; unsigned int *SectionTableAddr; // Load base address of Global Section Table SectionTableAddr = &__data_section_table; // Copy the data sections from flash to SRAM. while (SectionTableAddr < &__data_section_table_end) { LoadAddr = *SectionTableAddr++; ExeAddr = *SectionTableAddr++; SectionLen = *SectionTableAddr++; data_init(LoadAddr, ExeAddr, SectionLen); } // At this point, SectionTableAddr = &__bss_section_table; // Zero fill the bss segment while (SectionTableAddr < &__bss_section_table_end) { ExeAddr = *SectionTableAddr++; SectionLen = *SectionTableAddr++; bss_init(ExeAddr, SectionLen); } #if !defined (__USE_LPCOPEN) // LPCOpen init code deals with FP and VTOR initialisation #if defined (__VFP_FP__) && !defined (__SOFTFP__) /* * Code to enable the Cortex-M4 FPU only included * if appropriate build options have been selected. * Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C) */ // CPACR is located at address 0xE000ED88 asm("LDR.W R0, =0xE000ED88"); // Read CPACR asm("LDR R1, [R0]"); // Set bits 20-23 to enable CP10 and CP11 coprocessors asm(" ORR R1, R1, #(0xF << 20)"); // Write back the modified value to the CPACR asm("STR R1, [R0]"); #endif // (__VFP_FP__) && !(__SOFTFP__) // ****************************** // Check to see if we are running the code from a non-zero // address (eg RAM, external flash), in which case we need // to modify the VTOR register to tell the CPU that the // vector table is located at a non-0x0 address. // Note that we do not use the CMSIS register access mechanism, // as there is no guarantee that the project has been configured // to use CMSIS. unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08; if ((unsigned int *) g_pfnVectors != (unsigned int *) 0x00000000) { // CMSIS : SCB->VTOR = <address of vector table> *pSCB_VTOR = (unsigned int) g_pfnVectors; } #endif #if defined (__USE_CMSIS) || defined (__USE_LPCOPEN) SystemInit(); #endif #if defined (__cplusplus) // // Call C++ library initialisation // __libc_init_array(); #endif #if defined (__REDLIB__) // Call the Redlib library, which in turn calls main() __main() ; #else main(); #endif // // main() shouldn't return, but if it does, we'll just enter an infinite loop // while (1) { ; } }