int hal_btif_dma_hw_init(P_MTK_DMA_INFO_STR p_dma_info)
{
int i_ret = 0;
unsigned long base = p_dma_info->base;
P_DMA_VFIFO p_vfifo = p_dma_info->p_vfifo;
P_MTK_BTIF_DMA_VFIFO p_mtk_dma_vfifo = container_of(p_vfifo,
MTK_BTIF_DMA_VFIFO,
vfifo);
if (DMA_DIR_RX == p_dma_info->dir) {
/*Rx DMA*/
/*do hardware reset*/
// BTIF_SET_BIT(RX_DMA_RST(base), DMA_HARD_RST);
// BTIF_CLR_BIT(RX_DMA_RST(base), DMA_HARD_RST);
BTIF_SET_BIT(RX_DMA_RST(base), DMA_WARM_RST);
while((0x01 & BTIF_READ32(RX_DMA_EN(base))));
/*write vfifo base address to VFF_ADDR*/
btif_reg_sync_writel(p_vfifo->phy_addr, RX_DMA_VFF_ADDR(base));
/*write vfifo length to VFF_LEN*/
btif_reg_sync_writel(p_vfifo->vfifo_size, RX_DMA_VFF_LEN(base));
/*write wpt to VFF_WPT*/
btif_reg_sync_writel(p_mtk_dma_vfifo->wpt,
RX_DMA_VFF_WPT(base));
btif_reg_sync_writel(p_mtk_dma_vfifo->rpt,
RX_DMA_VFF_RPT(base));
/*write vff_thre to VFF_THRESHOLD*/
btif_reg_sync_writel(p_vfifo->thre, RX_DMA_VFF_THRE(base));
/*clear Rx DMA's interrupt status*/
BTIF_SET_BIT(RX_DMA_INT_FLAG(base),
RX_DMA_INT_DONE | RX_DMA_INT_THRE);
/*enable Rx IER by default*/
btif_rx_dma_ier_ctrl(p_dma_info, true);
} else {
/*Tx DMA*/
/*do hardware reset*/
// BTIF_SET_BIT(TX_DMA_RST(base), DMA_HARD_RST);
// BTIF_CLR_BIT(TX_DMA_RST(base), DMA_HARD_RST);
BTIF_SET_BIT(TX_DMA_RST(base), DMA_WARM_RST);
while((0x01 & BTIF_READ32(TX_DMA_EN(base))));
/*write vfifo base address to VFF_ADDR*/
btif_reg_sync_writel(p_vfifo->phy_addr, TX_DMA_VFF_ADDR(base));
/*write vfifo length to VFF_LEN*/
btif_reg_sync_writel(p_vfifo->vfifo_size, TX_DMA_VFF_LEN(base));
/*write wpt to VFF_WPT*/
btif_reg_sync_writel(p_mtk_dma_vfifo->wpt,
TX_DMA_VFF_WPT(base));
btif_reg_sync_writel(p_mtk_dma_vfifo->rpt,
TX_DMA_VFF_RPT(base));
/*write vff_thre to VFF_THRESHOLD*/
btif_reg_sync_writel(p_vfifo->thre, TX_DMA_VFF_THRE(base));
BTIF_CLR_BIT(TX_DMA_INT_FLAG(base), TX_DMA_INT_FLAG_MASK);
hal_btif_dma_ier_ctrl(p_dma_info, false);
}
return i_ret;
}
/*****************************************************************************
* FUNCTION
* hal_tx_dma_ier_ctrl
* DESCRIPTION
* BTIF Tx DMA's interrupt enable/disable
* PARAMETERS
* p_dma_info [IN] pointer to BTIF dma channel's information
* enable [IN] control if tx interrupt enabled or not
* RETURNS
* 0 means success, negative means fail
*****************************************************************************/
int hal_btif_dma_ier_ctrl(P_MTK_DMA_INFO_STR p_dma_info, bool en)
{
unsigned int i_ret = -1;
ENUM_DMA_DIR dir = p_dma_info->dir;
if (DMA_DIR_RX == dir) {
i_ret = btif_rx_dma_ier_ctrl(p_dma_info, en);
} else if (DMA_DIR_TX == dir) {
i_ret = btif_tx_dma_ier_ctrl(p_dma_info, en);
} else {
/*TODO: print error log*/
BTIF_ERR_FUNC("invalid DMA dma dir (%d)\n", dir);
i_ret = ERR_INVALID_PAR;
}
return i_ret;
}
