static int gpu_set_clock_pre(struct exynos_context *platform, int clk, bool is_up) { if (!platform) return -ENODEV; #if defined(CONFIG_EXYNOS5433_BTS) if (!is_up) { if (clk < platform->table[GPU_L4].clock) bts_scen_update(TYPE_G3D_SCENARIO, 0); else bts_scen_update(TYPE_G3D_SCENARIO, 1); } #endif /* CONFIG_EXYNOS5433_BTS */ return 0; }
static int gpu_set_clk_vol(struct kbase_device *kbdev, int clock, int voltage) { static int prev_clock = -1; struct exynos_context *platform = (struct exynos_context *)kbdev->platform_context; if (!platform) return -ENODEV; if ((clock > platform->table[platform->table_size-1].clock) || (clock < platform->table[0].clock)) { GPU_LOG(DVFS_ERROR, "Mismatch clock error (%d)\n", clock); return -1; } if (platform->voltage_margin) voltage = MAX(voltage + platform->voltage_margin, COLD_MINIMUM_VOL); if (clock > prev_clock) { gpu_set_voltage(platform, voltage); #ifdef CONFIG_DYNIMIC_ABB set_match_abb(ID_G3D, platform->devfreq_g3d_asv_abb[platform->step]); #endif gpu_set_clock(platform, clock); #if defined(CONFIG_EXYNOS5422_BTS) bts_scen_update(TYPE_G3D_FREQ, clock); #endif /* CONFIG_EXYNOS5422_BTS */ } else { #if defined(CONFIG_EXYNOS5422_BTS) bts_scen_update(TYPE_G3D_FREQ, clock); #endif /* CONFIG_EXYNOS5422_BTS */ gpu_set_clock(platform, clock); #ifdef CONFIG_DYNIMIC_ABB set_match_abb(ID_G3D, platform->devfreq_g3d_asv_abb[platform->step]); #endif gpu_set_voltage(platform, voltage); } GPU_LOG(DVFS_INFO, "[G3D]clk[%d -> %d], vol[%d + %d]\n", prev_clock, clock, voltage, platform->voltage_margin); gpu_dvfs_handler_control(kbdev, GPU_HANDLER_UPDATE_TIME_IN_STATE, prev_clock); prev_clock = clock; return 0; }