int
main(void)
{
u2_init();
// setup tx gpio bits for GPIOM_FPGA_1 -- fpga debug output
//hal_gpio_set_sels(GPIO_TX_BANK, "1111111111111111");
//hal_gpio_set_sels(GPIO_RX_BANK, "1111111111111111");
putstr("\ntx_only\n");
// Control LEDs
hal_set_leds(0x0, 0x3);
if (USE_BUFFER_INTERRUPT)
pic_register_handler(IRQ_BUFFER, buffer_irq_handler);
pic_register_handler(IRQ_OVERRUN, overrun_irq_handler);
pic_register_handler(IRQ_UNDERRUN, underrun_irq_handler);
//pic_register_handler(IRQ_TIMER, timer_irq_handler);
//hal_set_timeout(timer_delta);
ethernet_register_link_changed_callback(link_changed_callback);
ethernet_init();
// initialize double buffering state machine for DSP RX -> Ethernet
dbsm_init(&dsp_rx_sm, DSP_RX_BUF_0,
&dsp_rx_recv_args, &dsp_rx_send_args,
dbsm_nop_inspector);
// setup receive from ETH
// bp_receive_to_buf(CPU_RX_BUF, PORT_ETH, 1, 0, BP_LAST_LINE);
#if 0
if (hwconfig_simulation_p()){
// If we're simulating, pretend that we got a start command from the host
u2_mac_addr_t host = {{ 0x00, 0x0A, 0xE4, 0x3E, 0xD2, 0xD5 }};
start_rx_cmd(&host);
}
#endif
start_tx_transfers(); // send constant buffers to DSP TX
while(1){
if (!USE_BUFFER_INTERRUPT)
buffer_irq_handler(0);
}
}
int
main(void)
{
u2_init();
output_regs->led_src = 0x3; // h/w controls bottom two bits
clocks_enable_test_clk(true, 1);
putstr("\nMIMO Tx Slave\n");
cpu_tx_buf_dest_port = PORT_SERDES;
// ethernet_register_link_changed_callback(link_changed_callback);
// ethernet_init();
clocks_mimo_config(MC_WE_LOCK_TO_MIMO);
// puts("post clocks_mimo_config");
#if 0
// make bit 15 of Tx gpio's be a s/w output
hal_gpio_set_sel(GPIO_TX_BANK, 15, 's');
hal_gpio_set_ddr(GPIO_TX_BANK, 0x8000, 0x8000);
#endif
#if 0
output_regs->debug_mux_ctrl = 1;
hal_gpio_set_sels(GPIO_TX_BANK, "0000000000000000");
hal_gpio_set_sels(GPIO_RX_BANK, "0000000000000000");
hal_gpio_set_ddr(GPIO_TX_BANK, 0xffff, 0xffff);
hal_gpio_set_ddr(GPIO_RX_BANK, 0xffff, 0xffff);
#endif
// initialize double buffering state machine for ethernet -> DSP Tx
dbsm_init(&dsp_tx_sm, DSP_TX_BUF_0,
&dsp_tx_recv_args, &dsp_tx_send_args,
eth_pkt_inspector);
//output_regs->flush_icache = 1;
// initialize double buffering state machine for DSP RX -> Ethernet
if (FW_SETS_SEQNO){
dbsm_init(&dsp_rx_sm, DSP_RX_BUF_0,
&dsp_rx_recv_args, &dsp_rx_send_args,
fw_sets_seqno_inspector);
}
else {
dbsm_init(&dsp_rx_sm, DSP_RX_BUF_0,
&dsp_rx_recv_args, &dsp_rx_send_args,
dbsm_nop_inspector);
}
// puts("post dbsm_init's");
// tell app_common that this dbsm could be sending to the ethernet
ac_could_be_sending_to_eth = &dsp_rx_sm;
// program tx registers
setup_tx();
// puts("post setup_tx");
// kick off the state machine
dbsm_start(&dsp_tx_sm);
// puts("post dbsm_start");
//int which = 0;
while(1){
// hal_gpio_write(GPIO_TX_BANK, which, 0x8000);
// which ^= 0x8000;
buffer_irq_handler(0);
int pending = pic_regs->pending; // poll for under or overrun
if (pending & PIC_UNDERRUN_INT){
dbsm_handle_tx_underrun(&dsp_tx_sm);
pic_regs->pending = PIC_UNDERRUN_INT; // clear interrupt
putchar('U');
}
if (pending & PIC_OVERRUN_INT){
dbsm_handle_rx_overrun(&dsp_rx_sm);
pic_regs->pending = PIC_OVERRUN_INT; // clear pending interrupt
// FIXME Figure out how to handle this robustly.
// Any buffers that are emptying should be allowed to drain...
if (streaming_p){
// restart_streaming();
// FIXME report error
}
else {
// FIXME report error
}
putchar('O');
}
}
}
int
main(void)
{
u2_init();
putstr("\nFactory Test\n");
print_mac_addr(ethernet_mac_addr()->addr);
newline();
if(test_sd())
puts("SD OK\n");
else {
puts("SD FAIL\n");
// hal_finish();
//return 0;
}
if(test_ram())
puts("RAM OK\n");
else {
puts("RAM FAIL\n");
hal_finish();
return 0;
}
print_mac_addr(ethernet_mac_addr()->addr);
newline();
output_regs->led_src = 0x7; // make bottom 3 controlled by HW
ethernet_register_link_changed_callback(link_changed_callback);
ethernet_init();
clocks_enable_tx_dboard(true,1);
clocks_mimo_config(MC_WE_LOCK_TO_SMA);
#if 0
// make bit 15 of Tx gpio's be a s/w output
hal_gpio_set_sel(GPIO_TX_BANK, 15, 's');
hal_gpio_set_ddr(GPIO_TX_BANK, 0x8000, 0x8000);
#endif
output_regs->debug_mux_ctrl = 1;
#if 0
hal_gpio_set_sels(GPIO_TX_BANK, "1111111111111111");
hal_gpio_set_sels(GPIO_RX_BANK, "1111111111111111");
hal_gpio_set_ddr(GPIO_TX_BANK, 0xffff, 0xffff);
hal_gpio_set_ddr(GPIO_RX_BANK, 0xffff, 0xffff);
#endif
// initialize double buffering state machine for ethernet -> DSP Tx
dbsm_init(&dsp_tx_sm, DSP_TX_BUF_0,
&dsp_tx_recv_args, &dsp_tx_send_args,
eth_pkt_inspector);
// initialize double buffering state machine for DSP RX -> Ethernet
if (FW_SETS_SEQNO){
dbsm_init(&dsp_rx_sm, DSP_RX_BUF_0,
&dsp_rx_recv_args, &dsp_rx_send_args,
fw_sets_seqno_inspector);
}
else {
dbsm_init(&dsp_rx_sm, DSP_RX_BUF_0,
&dsp_rx_recv_args, &dsp_rx_send_args,
dbsm_nop_inspector);
}
// tell app_common that this dbsm could be sending to the ethernet
ac_could_be_sending_to_eth = &dsp_rx_sm;
// program tx registers
setup_tx();
// kick off the state machine
dbsm_start(&dsp_tx_sm);
//int which = 0;
while(1){
// hal_gpio_write(GPIO_TX_BANK, which, 0x8000);
// which ^= 0x8000;
buffer_irq_handler(0);
int pending = pic_regs->pending; // poll for under or overrun
if (pending & PIC_UNDERRUN_INT){
dbsm_handle_tx_underrun(&dsp_tx_sm);
pic_regs->pending = PIC_UNDERRUN_INT; // clear interrupt
putchar('U');
}
if (pending & PIC_OVERRUN_INT){
dbsm_handle_rx_overrun(&dsp_rx_sm);
pic_regs->pending = PIC_OVERRUN_INT; // clear pending interrupt
// FIXME Figure out how to handle this robustly.
// Any buffers that are emptying should be allowed to drain...
if (streaming_p){
// restart_streaming();
// FIXME report error
}
else {
// FIXME report error
}
putchar('O');
}
}
}