void
plog_cache_writeback(unsigned long start, long size)
{
long linesz, linemsk;
unsigned long end;
#if defined(CONFIG_BMIPS5000)
linesz = cpu_scache_line_size();
#else
linesz = cpu_dcache_line_size();
#endif
/*
* Set up the loop counters so the address is cache line aligned (do
* we really need to do that?) and the length is a multiple of the
* cache line size.
*/
linemsk = linesz - 1;
start &= ~linemsk;
size += linesz;
end = start + size;
while (start < end) {
#if defined(CONFIG_BMIPS5000)
cache_op(HitWbSc, start);
#else
cache_op(Hit_Writeback_D, start);
#endif
start += linesz;
}
__sync();
}
void flush_cache(unsigned long start_addr, unsigned long size)
{
unsigned long lsize = CONFIG_CACHELINE_SIZE;
unsigned long addr = start_addr & ~(lsize - 1);
unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
while (1) {
cache_op(Hit_Writeback_Inv_D, addr);
cache_op(Hit_Invalidate_I, addr);
if (addr == aend)
break;
addr += lsize;
}
}
void
caches_on(void)
{
uint32 config1;
uint start, end, size, lsize;
/* Save cache config */
config1 = MFC0(C0_CONFIG, 1);
icache_probe(config1, &size, &lsize);
icache_size = size;
ic_lsize = lsize;
dcache_probe(config1, &size, &lsize);
dcache_size = size;
dc_lsize = lsize;
/* If caches are not in the default state then
* presume that caches are already init'd
*/
if ((MFC0(C0_CONFIG, 0) & CONF_CM_CMASK) != CONF_CM_UNCACHED) {
blast_dcache();
blast_icache();
return;
}
/* init icache */
start = KSEG0;
end = (start + icache_size);
MTC0(C0_TAGLO, 0, 0);
MTC0(C0_TAGHI, 0, 0);
while (start < end) {
cache_op(start, Index_Store_Tag_I);
start += ic_lsize;
}
/* init dcache */
start = KSEG0;
end = (start + dcache_size);
MTC0(C0_TAGLO, 0, 0);
MTC0(C0_TAGHI, 0, 0);
while (start < end) {
cache_op(start, Index_Store_Tag_D);
start += dc_lsize;
}
/* Must be in KSEG1 to change cachability */
change_cachability = (void (*)(uint32)) KSEG1ADDR(_change_cachability);
change_cachability(CONF_CM_CACHABLE_NONCOHERENT);
}
static __cpuinit void ispram_store_data(unsigned int offset, unsigned int datalo, unsigned int datahi)
{
unsigned int errctl;
/* enable SPRAM tag access */
errctl = bis_c0_errctl(ERRCTL_SPRAM);
ehb();
#ifdef CONFIG_CPU_BIG_ENDIAN
write_c0_idatalo(datahi);
ehb();
write_c0_idatahi(datalo);
ehb();
#else
write_c0_idatalo(datalo);
ehb();
write_c0_idatahi(datahi);
ehb();
#endif
cache_op(MIPS34K_Index_Store_Data_I, CKSEG0|offset);
ehb();
write_c0_errctl(errctl);
ehb();
}
void flush_cache(ulong start_addr, ulong size)
{
unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
unsigned long addr = start_addr & ~(lsize - 1);
unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
/* aend will be miscalculated when size is zero, so we return here */
if (size == 0)
return;
while (1) {
cache_op(Hit_Writeback_Inv_D, addr);
cache_op(Hit_Invalidate_I, addr);
if (addr == aend)
break;
addr += lsize;
}
}
void flush_cache(ulong start_addr, ulong size)
{
unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
unsigned long addr = start_addr & ~(lsize - 1);
unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
/* aend will be miscalculated when size is zero, so we return here */
if (size == 0)
return;
while (1) {
cache_op(HIT_WRITEBACK_INV_D, addr);
cache_op(HIT_INVALIDATE_I, addr);
if (addr == aend)
break;
addr += lsize;
}
}
static unsigned long
probe_memsize(void)
{
#if !defined(CONFIG_MIPS_BRCM_SIM)
volatile uint32_t *addr = (volatile void *)KSEG1, *taddr;
uint32_t olddata;
long flags;
unsigned int i, memsize = 256;
printk("Probing system memory size... ");
local_irq_save(flags);
cache_op(Index_Writeback_Inv_D, KSEG0);
olddata = *addr;
/*
* Try to figure out where memory wraps around. If it does not
* wrap, assume 256MB
*/
for(i = 4; i <= 128; i <<= 1) {
taddr = (volatile void *)(KSEG1 + (i * 1048576));
*addr = MAGIC0;
if(*taddr == MAGIC0) {
*addr = MAGIC1;
if(*taddr == MAGIC1) {
memsize = i;
break;
}
}
}
*addr = olddata;
cache_op(Index_Writeback_Inv_D, KSEG0);
local_irq_restore(flags);
printk("found %u MB\n", memsize);
return(memsize * 1048576);
#else
/* Use fixed memory size (32MB) for simulation runs */
return(32 * 1048576);
#endif
}
void
blast_icache(void)
{
uint32 start, end;
start = KSEG0;
end = start + icache_size;
while (start < end) {
cache_op(start, Index_Invalidate_I);
start += ic_lsize;
}
}
void invalidate_dcache_range(ulong start_addr, ulong stop)
{
unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
unsigned long addr = start_addr & ~(lsize - 1);
unsigned long aend = (stop - 1) & ~(lsize - 1);
while (1) {
cache_op(Hit_Invalidate_D, addr);
if (addr == aend)
break;
addr += lsize;
}
}
void flush_dcache_range(ulong start_addr, ulong stop)
{
unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
unsigned long addr = start_addr & ~(lsize - 1);
unsigned long aend = (stop - 1) & ~(lsize - 1);
while (1) {
cache_op(HIT_WRITEBACK_INV_D, addr);
if (addr == aend)
break;
addr += lsize;
}
}
static __cpuinit void dspram_store_tag(unsigned int offset, unsigned int data)
{
unsigned int errctl;
/* enable SPRAM tag access */
errctl = bis_c0_errctl(ERRCTL_SPRAM);
ehb();
write_c0_dtaglo(data);
ehb();
cache_op(Index_Store_Tag_D, CKSEG0 | offset);
ehb();
write_c0_errctl(errctl);
ehb();
}
void
blast_dcache(void)
{
uint32 start, end;
start = KSEG0;
end = start + dcache_size;
while (start < end) {
BCM4710_DUMMY_RREG();
cache_op(start, Index_Writeback_Inv_D);
start += dc_lsize;
}
}
static inline unsigned int __init probe_ram_size(void)
{
volatile uint32_t *addr = (volatile void *)KSEG1, *taddr;
uint32_t olddata;
unsigned long flags;
unsigned int i, memsize = 256;
printk("Probing system memory size... ");
local_irq_save(flags);
cache_op(Hit_Writeback_Inv_D, KSEG0);
olddata = *addr;
/*
* Try to figure out where memory wraps around. If it does not
* wrap, assume 256MB
*/
for(i = 4; i <= 128; i <<= 1) {
taddr = (volatile void *)(KSEG1 + (i * 1048576));
*addr = MAGIC0;
if(*taddr == MAGIC0) {
*addr = MAGIC1;
if(*taddr == MAGIC1) {
memsize = i;
break;
}
}
}
*addr = olddata;
cache_op(Hit_Writeback_Inv_D, KSEG0);
local_irq_restore(flags);
printk("found %u MB\n", memsize);
return(memsize);
}
static inline unsigned int __init probe_ram_size(void)
{
unsigned long addr = KSEG1, taddr;
uint32_t olddata;
unsigned long flags;
unsigned int i, memsize = 256;
printk(KERN_INFO "Probing system memory size... ");
local_irq_save(flags);
cache_op(Hit_Writeback_Inv_D, KSEG0);
olddata = DEV_RD(addr);
/*
* Try to figure out where memory wraps around. If it does not
* wrap, assume 256MB
*/
for (i = 4; i <= 128; i <<= 1) {
taddr = KSEG1 + i * 1048576;
DEV_WR(addr, MAGIC0);
if (DEV_RD(taddr) == MAGIC0) {
DEV_WR(addr, MAGIC1);
if (DEV_RD(taddr) == MAGIC1) {
memsize = i;
break;
}
}
}
DEV_WR(addr, olddata);
cache_op(Hit_Writeback_Inv_D, KSEG0);
local_irq_restore(flags);
printk(KERN_CONT "found %u MB\n", memsize);
return memsize;
}
static __cpuinit unsigned int dspram_load_tag(unsigned int offset)
{
unsigned int data;
unsigned int errctl;
errctl = bis_c0_errctl(ERRCTL_SPRAM);
ehb();
cache_op(Index_Load_Tag_D, CKSEG0 | offset);
ehb();
data = read_c0_dtaglo();
ehb();
write_c0_errctl(errctl);
ehb();
return data;
}
static unsigned int ispram_load_tag(unsigned int offset)
{
unsigned int data;
unsigned int errctl;
/* enable SPRAM tag access */
errctl = bis_c0_errctl(ERRCTL_SPRAM);
ehb();
cache_op(Index_Load_Tag_I, CKSEG0 | offset);
ehb();
data = read_c0_taglo();
ehb();
write_c0_errctl(errctl);
ehb();
return data;
}
