void can_config(int mode)
{
can_reset(); //reset mcp
spi_chipselect(ENABLE); //enable slave
spi_tx_rx(WRITE_CMD);
//Enter config mode
//Send address of CAN CONTROL registerxFF because 0xXFH is mentioned
//0b10000000 to enter config mode
//be aware of potential delay while setting config_mode
can_write_reg(0xFF,0x80); //check config mode is achieved or not
spi_chipselect(DISABLE);
if(can_read_status()>>5 !=0x04)
{
printf("\n\rERROR UNABLE TO ENTER CONFIG MODE\n\r");
}
else
{
void can_set_id(short id){
char idh = (id & 0x03FF) >> 3;
char idl = (id & 0x0007);
/*
serial_printf("IDH=");
serial_print_hex(idh);
serial_printf(" -- IDL=");
serial_print_hex(idl);
serial_print_lf();
*/
can_write_reg(TXB0SIDH, idh);
can_write_bits(TXB0SIDL, idl << 5, 0xE0);
}
void can_load_byte(char input){
can_write_reg(TXB0D0+can_tx_pointer, input);
can_tx_pointer++;
}
////////////////////////////////////////////////////////////
// MCP2515 init routine
////////////////////////////////////////////////////////////
void can_init(short id){
delay_ms(25);
// We don't do a hardware reset, since we use the CLKOUT to clock the PIC
//mcp2515_rst_tris = 0;
//mcp2515_rst = 0;
//mcp2515_rst = 1;
// Do software reset instead
can_reset();
// We're in config mode now (auto after reset)
rx_message_pending = 0;
tx_message_pending = 0;
// Set physical layer configuration
//
// Fosc = 16MHz
// BRP = 7 (divide by 8)
// Sync Seg = 1TQ
// Prop Seg = 1TQ
// Phase Seg1 = 3TQ
// Phase Seg2 = 3TQ
//
// TQ = 2 * (1/Fosc) * (BRP+1)
// Bus speed = 1/(Total # of TQ) * TQ
// set BRP to div by 8
can_write_reg(CNF1, 0x07);
can_write_reg(CNF2, 0x90);
can_write_reg(CNF3, 0x02);
// Configure Receive buffer 0 Mask and Filters
// Receive buffer 0 will not be used
can_write_reg(RXM0SIDH, 0xFF);
can_write_reg(RXM0SIDL, 0xFF);
can_write_reg(RXF0SIDH, 0xFF);
can_write_reg(RXF0SIDL, 0xFF);
// Configure Receive Buffer 1 Mask and Filters
can_write_reg(RXF1SIDH, 0xFF);
can_write_reg(RXF1SIDL, 0xFF);
can_write_reg(RXM1SIDH, 0x00); // was FF
can_write_reg(RXM1SIDL, 0x00);
// Initialize Filter 2 to match x0 bBaseRecID
can_write_reg(RXF2SIDH, CAN_RX_ID);
can_write_reg(RXF2SIDL, 0x00); //; Make sure EXIDE bit (bit 3) is set correctly in filter
// Initialize Filter 3 to match x1
can_write_reg(RXF3SIDH, CAN_RX_ID + 1);
can_write_reg(RXF3SIDL, 0x00);
// Initialize Filter 4 to match x2
can_write_reg(RXF4SIDH, CAN_RX_ID + 2);
can_write_reg(RXF4SIDL, 0x00);
// Initialize Filter 5 to match x3
can_write_reg(RXF5SIDH, CAN_RX_ID + 3);
can_write_reg(RXF5SIDL, 0x00);
// Disable all MCP2510 Interrupts
can_write_reg(CANINTE, 0x00);
// Set the TX id
can_set_id(id);
// Set normal mode (not loopback)
//can_set_loopback_mode();
can_set_normal_mode();
// Disable filter and mask on buffer 0
can_write_bits(RXB0CTRL, 0x60, 0x60);
}
