/* selected cbmem can be initialized early in ramstage. Additionally, that
* means cbmem console can be reinitialized early as well. The post_device
* function is empty since cbmem was initialized early in ramstage. */
static void init_cbmem_pre_device(void *unused)
{
cbmem_initialize();
#if CONFIG_CONSOLE_CBMEM
cbmemc_reinit();
#endif /* CONFIG_CONSOLE_CBMEM */
}
static void init_cbmem_post_device(void *unused)
{
if (acpi_is_wakeup())
cbmem_initialize();
else
cbmem_initialize_empty();
}
int cbmem_recovery(int is_wakeup)
{
int rv = 0;
if (!is_wakeup)
cbmem_initialize_empty();
else
rv = cbmem_initialize();
return rv;
}
void main(unsigned long bist)
{
int cbmem_was_initted;
/* init_timer(); */
post_code(0x05);
i82801ix_early_init();
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
//print_pci_devices();
//dump_pci_devices();
cbmem_was_initted = !cbmem_initialize();
timestamp_init(rdtsc());
timestamp_add_now(TS_START_ROMSTAGE);
}
void raminit(struct mrc_params *mp, int prev_sleep_state)
{
int ret;
mrc_wrapper_entry_t mrc_entry;
const struct mrc_saved_data *cache;
/* Fill in default entries. */
mp->version = MRC_PARAMS_VER;
mp->console_out = &send_to_console;
mp->prev_sleep_state = prev_sleep_state;
mp->rmt_enabled = IS_ENABLED(CONFIG_MRC_RMT);
/* Default to 2GiB IO hole. */
if (!mp->io_hole_mb)
mp->io_hole_mb = 2048;
if (vboot_recovery_mode_enabled()) {
printk(BIOS_DEBUG, "Recovery mode: not using MRC cache.\n");
} else if (!mrc_cache_get_current(&cache)) {
mp->saved_data_size = cache->size;
mp->saved_data = &cache->data[0];
} else if (prev_sleep_state == ACPI_S3) {
/* If waking from S3 and no cache then. */
printk(BIOS_DEBUG, "No MRC cache found in S3 resume path.\n");
post_code(POST_RESUME_FAILURE);
reset_system();
} else {
printk(BIOS_DEBUG, "No MRC cache found.\n");
#if CONFIG_EC_GOOGLE_CHROMEEC
if (prev_sleep_state == ACPI_S0) {
/* Ensure EC is running RO firmware. */
google_chromeec_check_ec_image(EC_IMAGE_RO);
}
#endif
}
/* Determine if mrc.bin is in the cbfs. */
if (cbfs_boot_map_with_leak("mrc.bin", CBFS_TYPE_MRC, NULL) == NULL) {
printk(BIOS_DEBUG, "Couldn't find mrc.bin\n");
return;
}
/*
* The entry point is currently the first instruction. Handle the
* case of an ELF file being put in the cbfs by setting the entry
* to the CONFIG_MRC_BIN_ADDRESS.
*/
mrc_entry = (void *)(uintptr_t)CONFIG_MRC_BIN_ADDRESS;
if (mp->mainboard.dram_info_location == DRAM_INFO_SPD_SMBUS)
enable_smbus();
ret = mrc_entry(mp);
print_dram_info();
if (prev_sleep_state != ACPI_S3) {
cbmem_initialize_empty();
} else if (cbmem_initialize()) {
#if CONFIG_HAVE_ACPI_RESUME
printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n");
/* Failed S3 resume, reset to come up cleanly */
reset_system();
#endif
}
printk(BIOS_DEBUG, "MRC Wrapper returned %d\n", ret);
printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", mp->data_to_save,
mp->data_to_save_size);
if (mp->data_to_save != NULL && mp->data_to_save_size > 0)
mrc_cache_stash_data(mp->data_to_save, mp->data_to_save_size);
}
void romstage_common(const struct romstage_params *params)
{
int boot_mode;
int wake_from_s3;
struct romstage_handoff *handoff;
#if CONFIG_COLLECT_TIMESTAMPS
uint64_t start_romstage_time;
uint64_t before_dram_time;
uint64_t after_dram_time;
uint64_t base_time =
(uint64_t)pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) << 32 ||
pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc);
#endif
#if CONFIG_COLLECT_TIMESTAMPS
start_romstage_time = timestamp_get();
#endif
if (params->bist == 0)
enable_lapic();
wake_from_s3 = early_pch_init(params->gpio_map, params->rcba_config);
#if CONFIG_EC_GOOGLE_CHROMEEC
/* Ensure the EC is in the right mode for recovery */
google_chromeec_early_init();
#endif
/* Halt if there was a built in self test failure */
report_bist_failure(params->bist);
/* Perform some early chipset initialization required
* before RAM initialization can work
*/
haswell_early_initialization(HASWELL_MOBILE);
printk(BIOS_DEBUG, "Back from haswell_early_initialization()\n");
if (wake_from_s3) {
#if CONFIG_HAVE_ACPI_RESUME
printk(BIOS_DEBUG, "Resume from S3 detected.\n");
#else
printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
wake_from_s3 = 0;
#endif
}
/* There are hard coded assumptions of 2 meaning s3 wake. Normalize
* the users of the 2 literal here based off wake_from_s3. */
boot_mode = wake_from_s3 ? 2 : 0;
/* Prepare USB controller early in S3 resume */
if (wake_from_s3)
enable_usb_bar();
post_code(0x3a);
params->pei_data->boot_mode = boot_mode;
#if CONFIG_COLLECT_TIMESTAMPS
before_dram_time = timestamp_get();
#endif
report_platform_info();
if (params->copy_spd != NULL)
params->copy_spd(params->pei_data);
sdram_initialize(params->pei_data);
#if CONFIG_COLLECT_TIMESTAMPS
after_dram_time = timestamp_get();
#endif
post_code(0x3b);
intel_early_me_status();
quick_ram_check();
post_code(0x3e);
if (!wake_from_s3) {
cbmem_initialize_empty();
/* Save data returned from MRC on non-S3 resumes. */
save_mrc_data(params->pei_data);
} else if (cbmem_initialize()) {
#if CONFIG_HAVE_ACPI_RESUME
/* Failed S3 resume, reset to come up cleanly */
reset_system();
#endif
}
handoff = romstage_handoff_find_or_add();
if (handoff != NULL)
handoff->s3_resume = wake_from_s3;
else
printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
post_code(0x3f);
#if CONFIG_CHROMEOS
init_chromeos(boot_mode);
#endif
#if CONFIG_COLLECT_TIMESTAMPS
timestamp_init(base_time);
timestamp_add(TS_START_ROMSTAGE, start_romstage_time );
timestamp_add(TS_BEFORE_INITRAM, before_dram_time );
timestamp_add(TS_AFTER_INITRAM, after_dram_time );
timestamp_add_now(TS_END_ROMSTAGE);
#endif
}
void romstage_common(const struct romstage_params *params)
{
int boot_mode;
int wake_from_s3;
timestamp_init(get_initial_timestamp());
timestamp_add_now(TS_START_ROMSTAGE);
if (params->bist == 0)
enable_lapic();
wake_from_s3 = early_pch_init(params->gpio_map, params->rcba_config);
#if CONFIG_EC_GOOGLE_CHROMEEC
/* Ensure the EC is in the right mode for recovery */
google_chromeec_early_init();
#endif
/* Halt if there was a built in self test failure */
report_bist_failure(params->bist);
/* Perform some early chipset initialization required
* before RAM initialization can work
*/
haswell_early_initialization(HASWELL_MOBILE);
printk(BIOS_DEBUG, "Back from haswell_early_initialization()\n");
if (wake_from_s3) {
#if CONFIG_HAVE_ACPI_RESUME
printk(BIOS_DEBUG, "Resume from S3 detected.\n");
#else
printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
wake_from_s3 = 0;
#endif
}
/* There are hard coded assumptions of 2 meaning s3 wake. Normalize
* the users of the 2 literal here based off wake_from_s3. */
boot_mode = wake_from_s3 ? 2 : 0;
/* Prepare USB controller early in S3 resume */
if (wake_from_s3)
enable_usb_bar();
post_code(0x3a);
params->pei_data->boot_mode = boot_mode;
timestamp_add_now(TS_BEFORE_INITRAM);
report_platform_info();
if (params->copy_spd != NULL)
params->copy_spd(params->pei_data);
sdram_initialize(params->pei_data);
timestamp_add_now(TS_AFTER_INITRAM);
post_code(0x3b);
intel_early_me_status();
quick_ram_check();
post_code(0x3e);
if (!wake_from_s3) {
cbmem_initialize_empty();
/* Save data returned from MRC on non-S3 resumes. */
save_mrc_data(params->pei_data);
} else if (cbmem_initialize()) {
#if CONFIG_HAVE_ACPI_RESUME
/* Failed S3 resume, reset to come up cleanly */
reset_system();
#endif
}
romstage_handoff_init(wake_from_s3);
post_code(0x3f);
if (IS_ENABLED(CONFIG_LPC_TPM))
init_tpm(wake_from_s3);
}
void hardwaremain(int boot_complete)
{
struct lb_memory *lb_mem;
void *payload;
timestamp_stash(TS_START_RAMSTAGE);
post_code(POST_ENTRY_RAMSTAGE);
#if CONFIG_COVERAGE
coverage_init();
#endif
/* console_init() MUST PRECEDE ALL printk()! */
console_init();
post_code(POST_CONSOLE_READY);
printk(BIOS_NOTICE, "coreboot-%s%s %s %s...\n",
coreboot_version, coreboot_extra_version, coreboot_build,
(boot_complete)?"rebooting":"booting");
post_code(POST_CONSOLE_BOOT_MSG);
/* If we have already booted attempt a hard reboot */
if (boot_complete) {
hard_reset();
}
/* FIXME: Is there a better way to handle this? */
init_timer();
timestamp_stash(TS_DEVICE_ENUMERATE);
/* Initialize chips early, they might disable unused devices. */
dev_initialize_chips();
/* Find the devices we don't have hard coded knowledge about. */
dev_enumerate();
post_code(POST_DEVICE_ENUMERATION_COMPLETE);
timestamp_stash(TS_DEVICE_CONFIGURE);
/* Now compute and assign the bus resources. */
dev_configure();
post_code(POST_DEVICE_CONFIGURATION_COMPLETE);
timestamp_stash(TS_DEVICE_ENABLE);
/* Now actually enable devices on the bus */
dev_enable();
post_code(POST_DEVICES_ENABLED);
timestamp_stash(TS_DEVICE_INITIALIZE);
/* And of course initialize devices on the bus */
dev_initialize();
post_code(POST_DEVICES_INITIALIZED);
timestamp_stash(TS_DEVICE_DONE);
cbmem_initialize();
#if CONFIG_CONSOLE_CBMEM
cbmemc_reinit();
#endif
timestamp_sync();
#if CONFIG_HAVE_ACPI_RESUME
suspend_resume();
post_code(0x8a);
#endif
timestamp_add_now(TS_CBMEM_POST);
if (cbmem_post_handling)
cbmem_post_handling();
timestamp_add_now(TS_WRITE_TABLES);
/* Now that we have collected all of our information
* write our configuration tables.
*/
lb_mem = write_tables();
timestamp_add_now(TS_LOAD_PAYLOAD);
payload = cbfs_load_payload(CBFS_DEFAULT_MEDIA,
CONFIG_CBFS_PREFIX "/payload");
if (! payload)
die("Could not find a payload\n");
selfboot(lb_mem, payload);
printk(BIOS_EMERG, "Boot failed");
}
/* selected cbmem can be initialized early in ramstage. Additionally, that
* means cbmem console can be reinitialized early as well. The post_device
* function is empty since cbmem was initialized early in ramstage. */
static void init_cbmem_pre_device(void *unused)
{
cbmem_initialize();
}
