static void __init sun8i_a33_ccu_setup(struct device_node *node) { void __iomem *reg; u32 val; reg = of_io_request_and_map(node, 0, of_node_full_name(node)); if (IS_ERR(reg)) { pr_err("%s: Could not map the clock registers\n", of_node_full_name(node)); return; } /* Force the PLL-Audio-1x divider to 4 */ val = readl(reg + SUN8I_A33_PLL_AUDIO_REG); val &= ~GENMASK(19, 16); writel(val | (3 << 16), reg + SUN8I_A33_PLL_AUDIO_REG); /* Force PLL-MIPI to MIPI mode */ val = readl(reg + SUN8I_A33_PLL_MIPI_REG); val &= ~BIT(16); writel(val, reg + SUN8I_A33_PLL_MIPI_REG); sunxi_ccu_probe(node, reg, &sun8i_a33_ccu_desc); ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk, &sun8i_a33_cpu_nb); }
static int sun8i_r40_ccu_probe(struct platform_device *pdev) { struct resource *res; struct regmap *regmap; void __iomem *reg; u32 val; int ret; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); reg = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(reg)) return PTR_ERR(reg); /* Force the PLL-Audio-1x divider to 4 */ val = readl(reg + SUN8I_R40_PLL_AUDIO_REG); val &= ~GENMASK(19, 16); writel(val | (3 << 16), reg + SUN8I_R40_PLL_AUDIO_REG); /* Force PLL-MIPI to MIPI mode */ val = readl(reg + SUN8I_R40_PLL_MIPI_REG); val &= ~BIT(16); writel(val, reg + SUN8I_R40_PLL_MIPI_REG); /* Force OHCI 12M parent to 12M divided from 48M */ val = readl(reg + SUN8I_R40_USB_CLK_REG); val &= ~GENMASK(25, 20); writel(val, reg + SUN8I_R40_USB_CLK_REG); /* * Force SYS 32k (otherwise known as LOSC throughout the CCU) * clock parent to LOSC output from RTC module instead of the * CCU's internal RC oscillator divided output. */ writel(SUN8I_R40_SYS_32K_CLK_KEY | BIT(8), reg + SUN8I_R40_SYS_32K_CLK_REG); regmap = devm_regmap_init_mmio(&pdev->dev, reg, &sun8i_r40_ccu_regmap_config); if (IS_ERR(regmap)) return PTR_ERR(regmap); ret = sunxi_ccu_probe(pdev->dev.of_node, reg, &sun8i_r40_ccu_desc); if (ret) return ret; /* Gate then ungate PLL CPU after any rate changes */ ccu_pll_notifier_register(&sun8i_r40_pll_cpu_nb); /* Reparent CPU during PLL CPU rate changes */ ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk, &sun8i_r40_cpu_nb); return 0; }
static void __init sun8i_r40_ccu_setup(struct device_node *node) { void __iomem *reg; u32 val; reg = of_io_request_and_map(node, 0, of_node_full_name(node)); if (IS_ERR(reg)) { pr_err("%s: Could not map the clock registers\n", of_node_full_name(node)); return; } /* Force the PLL-Audio-1x divider to 4 */ val = readl(reg + SUN8I_R40_PLL_AUDIO_REG); val &= ~GENMASK(19, 16); writel(val | (3 << 16), reg + SUN8I_R40_PLL_AUDIO_REG); /* Force PLL-MIPI to MIPI mode */ val = readl(reg + SUN8I_R40_PLL_MIPI_REG); val &= ~BIT(16); writel(val, reg + SUN8I_R40_PLL_MIPI_REG); /* Force OHCI 12M parent to 12M divided from 48M */ val = readl(reg + SUN8I_R40_USB_CLK_REG); val &= ~GENMASK(25, 20); writel(val, reg + SUN8I_R40_USB_CLK_REG); sunxi_ccu_probe(node, reg, &sun8i_r40_ccu_desc); /* Gate then ungate PLL CPU after any rate changes */ ccu_pll_notifier_register(&sun8i_r40_pll_cpu_nb); /* Reparent CPU during PLL CPU rate changes */ ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk, &sun8i_r40_cpu_nb); }