void __init nino_irq_setup(void)
{
extern asmlinkage void ninoIRQ(void);
unsigned int i;
/* Disable all hardware interrupts */
change_cp0_status(ST0_IM, 0x00);
/* Initialize IRQ vector table */
//init_generic_irq();
/* Initialize IRQ action handlers */
for (i = 0; i < 16; i++) {
hw_irq_controller *handler = NULL;
handler = &irq_type;
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = 0;
irq_desc[i].depth = 1;
irq_desc[i].handler = handler;
}
/* Set up the external interrupt exception vector */
set_except_vector(0, ninoIRQ);
/* Enable all interrupts */
change_cp0_status(ST0_IM, ALLINTS);
}
void __init nino_irq_setup(void)
{
extern asmlinkage void ninoIRQ(void);
extern void init_generic_irq(void);
unsigned int i;
/* Disable all hardware interrupts */
change_cp0_status(ST0_IM, 0x00);
/* Clear interrupts */
outl(0xffffffff, TX3912_INT1_CLEAR);
outl(0xffffffff, TX3912_INT2_CLEAR);
outl(0xffffffff, TX3912_INT3_CLEAR);
outl(0xffffffff, TX3912_INT4_CLEAR);
outl(0xffffffff, TX3912_INT5_CLEAR);
/*
* Disable all PR31700 interrupts. We let the various
* device drivers in the system register themselves
* and set the proper hardware bits.
*/
outl(0x00000000, TX3912_INT1_ENABLE);
outl(0x00000000, TX3912_INT2_ENABLE);
outl(0x00000000, TX3912_INT3_ENABLE);
outl(0x00000000, TX3912_INT4_ENABLE);
outl(0x00000000, TX3912_INT5_ENABLE);
/* Initialize IRQ vector table */
init_generic_irq();
/* Initialize IRQ action handlers */
for (i = 0; i < 16; i++) {
hw_irq_controller *handler = NULL;
if (i == 0 || i == 3)
handler = &irq6_type;
else
handler = &irq4_type;
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = 0;
irq_desc[i].depth = 1;
irq_desc[i].handler = handler;
}
/* Set up the external interrupt exception vector */
set_except_vector(0, ninoIRQ);
/* Enable high priority interrupts */
outl(TX3912_INT6_ENABLE_GLOBALEN | TX3912_INT6_ENABLE_HIGH_PRIORITY,
TX3912_INT6_ENABLE);
/* Enable all interrupts */
change_cp0_status(ST0_IM, ALLINTS);
}
void vr4122_restart(char *command)
{
change_cp0_status((ST0_BEV | ST0_ERL), (ST0_BEV | ST0_ERL));
change_cp0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
flush_cache_all();
write_32bit_cp0_register(CP0_WIRED, 0);
__asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
}
void __init ExceptionToIrq_setup(void)
{
extern asmlinkage void IRQ_finder(void);
unsigned int i;
/* Disable all hardware interrupts */
change_cp0_status(ST0_IM, 0x00);
/* Set up the external interrupt exception vector */
/* First exception is Interrupt*/
set_except_vector(0, IRQ_finder);
/* Enable all interrupts */
change_cp0_status(ST0_IM, ALLINTS);
// prom_printf("###");
}
static void __init nino_irq_setup(void)
{
unsigned int tmp;
/* Turn all interrupts off */
IntEnable1 = 0;
IntEnable2 = 0;
IntEnable3 = 0;
IntEnable4 = 0;
IntEnable5 = 0;
IntEnable6 = 0;
/* Clear all interrupts */
IntClear1 = 0xffffffff;
IntClear2 = 0xffffffff;
IntClear3 = 0xffffffff;
IntClear4 = 0xffffffff;
IntClear5 = 0xffffffff;
IntClear6 = 0xffffffff;
/*
* Enable only the interrupts for the UART and negative
* edge (1-to-0) triggered multi-function I/O pins.
*/
change_cp0_status(ST0_BEV, 0);
tmp = read_32bit_cp0_register(CP0_STATUS);
change_cp0_status(ST0_IM, tmp | IE_IRQ2 | IE_IRQ4);
/* Register the global interrupt handler */
set_except_vector(0, nino_handle_int);
#ifdef CONFIG_REMOTE_DEBUG
if (remote_debug) {
set_debug_traps();
breakpoint();
}
#endif
}
static void __init ddb_time_init(struct irqaction *irq)
{
/* set the clock to 1 Hz */
nile4_out32(NILE4_T2CTRL, 1000000);
/* enable the General-Purpose Timer */
nile4_out32(NILE4_T2CTRL + 4, 0x00000001);
/* reset timer */
nile4_out32(NILE4_T2CNTR, 0);
/* enable interrupt */
nile4_enable_irq(NILE4_INT_GPT);
i8259_setup_irq(nile4_to_irq(NILE4_INT_GPT), irq);
change_cp0_status(ST0_IM,
IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4);
}
static void __init cobalt_timer_setup(struct irqaction *irq)
{
/* Load timer value for 150 Hz */
cobalt_calibrate_timer();
setup_irq(0, irq);
change_cp0_status(ST0_IM, IE_IRQ4 | IE_IRQ3 | IE_IRQ2 | IE_IRQ1 | IE_IRQ0);
/* Enable timer ints */
*((volatile unsigned long *) GALILEO_TIMER_CTRL) =
(unsigned long) (GALILEO_ENTC0 | GALILEO_SELTC0);
/* Unmask timer int */
*((volatile unsigned long *) GALILEO_CPU_MASK) = (unsigned long) 0x00000100;
}
void __init brcm_irq_setup(void)
{
extern asmlinkage void brcmIRQ(void);
/* In 2.4.3 Kernel this was done in trap_init. In 2.4.17 it was
* moved to SMP code, which is only used by MIPS64. In other words
* Linux is free, you get what you pay for */
clear_cp0_status(ST0_BEV);
set_except_vector(0, brcmIRQ);
change_cp0_status(ST0_IM, ALLINTS_NOTIMER);
#ifdef CONFIG_REMOTE_DEBUG
rs_kgdb_hook(0);
#endif
}