void tms32082_mp_device::execute_run()
{
while (m_icount > 0)
{
m_pc = m_fetchpc;
check_interrupts();
debugger_instruction_hook(this, m_pc);
m_ir = fetch();
execute();
m_tcount--;
if (m_tcount < 0)
{
// TODO: timer interrupt
m_tcount = m_tscale;
}
m_icount--;
};
return;
}
int mc68901_device::get_vector()
{
int ch;
for (ch = 15; ch >= 0; ch--)
{
if (BIT(m_imr, ch) && BIT(m_ipr, ch))
{
if (m_vr & VR_S)
{
/* set interrupt-in-service bit */
m_isr |= (1 << ch);
}
/* clear interrupt pending bit */
m_ipr &= ~(1 << ch);
check_interrupts();
return (m_vr & 0xf0) | ch;
}
}
return M68K_INT_ACK_SPURIOUS;
}
void lr35902_cpu_device::execute_run()
{
do
{
if ( m_execution_state ) {
UINT8 x;
/* Execute instruction */
switch( m_op ) {
#include "opc_main.inc"
default:
// actually this should lock up the cpu!
logerror("LR35902: Illegal opcode $%02X @ %04X\n", m_op, m_PC);
break;
}
} else {
/* Fetch and count cycles */
check_interrupts();
debugger_instruction_hook(this, m_PC);
if ( m_enable & HALTED ) {
cycles_passed( 4 );
m_execution_state = 1;
} else {
m_op = mem_read_byte( m_PC++ );
if ( m_handle_halt_bug ) {
m_PC--;
m_handle_halt_bug = false;
}
}
}
m_execution_state ^= 1;
} while (m_icount > 0);
}
//-------------------------------------------------
// z80daisy_irq_ack - interrupt acknowledge
//-------------------------------------------------
int z80sio_device::z80daisy_irq_ack()
{
int i;
LOGINT("%s %s \n",FUNCNAME, tag());
// loop over all interrupt sources
for (i = 0; i < 8; i++)
{
// find the first channel with an interrupt requested
if (m_int_state[i] & Z80_DAISY_INT)
{
// clear interrupt, switch to the IEO state, and update the IRQs
m_int_state[i] = Z80_DAISY_IEO;
m_chanA->m_rr0 &= ~z80sio_channel::RR0_INTERRUPT_PENDING;
check_interrupts();
//LOG("%s %s \n",FUNCNAME, tag(), m_chanB->m_rr2);
return m_chanB->m_rr2;
}
}
//logerror("z80sio_irq_ack: failed to find an interrupt to ack!\n");
return m_chanB->m_rr2;
}
void lr35902_cpu_device::execute_run()
{
do
{
if ( m_execution_state ) {
UINT8 x;
/* Execute instruction */
switch( m_op ) {
#include "opc_main.h"
}
} else {
/* Fetch and count cycles */
check_interrupts();
debugger_instruction_hook(this, m_PC);
if ( m_enable & HALTED ) {
cycles_passed( 4 );
m_execution_state = 1;
} else {
m_op = mem_read_byte( m_PC++ );
if ( m_doHALTbug ) {
m_PC--;
m_doHALTbug = 0;
}
}
}
m_execution_state ^= 1;
} while (m_icount > 0);
}
READ8_DEVICE_HANDLER_TRAMPOLINE(acia6850, acia6850_data_r)
{
m_status &= ~(ACIA6850_STATUS_RDRF | ACIA6850_STATUS_IRQ | ACIA6850_STATUS_PE);
if (m_status_read)
{
int dcd = devcb_call_read_line(&m_in_dcd_func);
m_status_read = 0;
m_status &= ~(ACIA6850_STATUS_OVRN | ACIA6850_STATUS_DCD);
if (dcd)
{
m_status |= ACIA6850_STATUS_DCD;
}
}
if (m_overrun == 1)
{
m_status |= ACIA6850_STATUS_OVRN;
m_overrun = 0;
}
check_interrupts();
return m_rdr;
}
int z80sti_device::z80daisy_irq_ack()
{
int i;
// loop over all interrupt sources
for (i = 15; i >= 0; i--)
{
// find the first channel with an interrupt requested
if (m_int_state[i] & Z80_DAISY_INT)
{
UINT8 vector = (m_pvr & 0xe0) | INT_VECTOR[i];
// clear interrupt, switch to the IEO state, and update the IRQs
m_int_state[i] = Z80_DAISY_IEO;
// clear interrupt pending register bit
m_ipr &= ~(1 << i);
// set interrupt in-service register bit
m_isr |= (1 << i);
check_interrupts();
LOG(("Z80STI '%s' Interrupt Acknowledge Vector: %02x\n", tag(), vector));
return vector;
}
}
logerror("z80sti_irq_ack: failed to find an interrupt to ack!\n");
return 0;
}
void z80sti_device::z80daisy_irq_reti()
{
int i;
LOG(("Z80STI '%s' Return from Interrupt\n", tag()));
// loop over all interrupt sources
for (i = 15; i >= 0; i--)
{
// find the first channel with an IEO pending
if (m_int_state[i] & Z80_DAISY_IEO)
{
// clear the IEO state and update the IRQs
m_int_state[i] &= ~Z80_DAISY_IEO;
// clear interrupt in-service register bit
m_isr &= ~(1 << i);
check_interrupts();
return;
}
}
logerror("z80sti_irq_reti: failed to find an interrupt to clear IEO on!\n");
}
int z80dart_device::z80daisy_irq_ack()
{
int i;
LOG(("Z80DART \"%s\" Interrupt Acknowledge\n", tag()));
// loop over all interrupt sources
for (i = 0; i < 8; i++)
{
// find the first channel with an interrupt requested
if (m_int_state[i] & Z80_DAISY_INT)
{
// clear interrupt, switch to the IEO state, and update the IRQs
m_int_state[i] = Z80_DAISY_IEO;
m_chanA->m_rr[0] &= ~z80dart_channel::RR0_INTERRUPT_PENDING;
check_interrupts();
LOG(("Z80DART \"%s\" : Interrupt Acknowledge Vector %02x\n", tag(), m_chanB->m_rr[2]));
return m_chanB->m_rr[2];
}
}
//logerror("z80dart_irq_ack: failed to find an interrupt to ack!\n");
return m_chanB->m_rr[2];
}
void z80dart_device::take_interrupt(int priority)
{
m_int_state[priority] |= Z80_DAISY_INT;
m_channel[Z80DART_CH_A].m_rr[0] |= Z80DART_RR0_INTERRUPT_PENDING;
// check for interrupt
check_interrupts();
}
void z80dart_device::reset_interrupts()
{
for (auto & elem : m_int_state)
{
elem = 0;
}
check_interrupts();
}
void z80dart_device::reset_interrupts()
{
for (int i = 0; i < 8; i++)
{
m_int_state[i] = 0;
}
check_interrupts();
}
static void tms_interrupt(int irq)
{
if ((tms.imr & (1 << irq)) != 0)
{
tms.ifr |= 1 << irq;
}
check_interrupts();
}
static void tms_interrupt(tms32051_state *cpustate, int irq)
{
if ((cpustate->imr & (1 << irq)) != 0)
{
cpustate->ifr |= 1 << irq;
}
check_interrupts(cpustate);
}
void z80sti_device::take_interrupt(int level)
{
// set interrupt pending register bit
m_ipr |= 1 << level;
// trigger interrupt
m_int_state[level] |= Z80_DAISY_INT;
check_interrupts();
}
//-------------------------------------------------
// reset_interrupts -
//-------------------------------------------------
void z80sio_device::reset_interrupts()
{
LOGINT("%s %s \n",FUNCNAME, tag());
// reset internal interrupt sources
for (auto & elem : m_int_state)
{
elem = 0;
}
check_interrupts();
}
//-------------------------------------------------
// reset_interrupts -
//-------------------------------------------------
void z80sio_device::reset_interrupts()
{
LOG(("%s %s \n",FUNCNAME, tag()));
// reset internal interrupt sources
for (int i = 0; i < 8; i++)
{
m_int_state[i] = 0;
}
check_interrupts();
}
void z80dart_device::device_reset()
{
LOG(("Z80DART \"%s\" Reset\n", tag()));
for (int channel = Z80DART_CH_A; channel <= Z80DART_CH_B; channel++)
{
m_channel[channel].reset();
}
check_interrupts();
}
void xtensa_cpu_do_interrupt(CPUState *cs)
{
XtensaCPU *cpu = XTENSA_CPU(cs);
CPUXtensaState *env = &cpu->env;
if (env->exception_index == EXC_IRQ) {
qemu_log_mask(CPU_LOG_INT,
"%s(EXC_IRQ) level = %d, cintlevel = %d, "
"pc = %08x, a0 = %08x, ps = %08x, "
"intset = %08x, intenable = %08x, "
"ccount = %08x\n",
__func__, env->pending_irq_level, xtensa_get_cintlevel(env),
env->pc, env->regs[0], env->sregs[PS],
env->sregs[INTSET], env->sregs[INTENABLE],
env->sregs[CCOUNT]);
handle_interrupt(env);
}
switch (env->exception_index) {
case EXC_WINDOW_OVERFLOW4:
case EXC_WINDOW_UNDERFLOW4:
case EXC_WINDOW_OVERFLOW8:
case EXC_WINDOW_UNDERFLOW8:
case EXC_WINDOW_OVERFLOW12:
case EXC_WINDOW_UNDERFLOW12:
case EXC_KERNEL:
case EXC_USER:
case EXC_DOUBLE:
case EXC_DEBUG:
qemu_log_mask(CPU_LOG_INT, "%s(%d) "
"pc = %08x, a0 = %08x, ps = %08x, ccount = %08x\n",
__func__, env->exception_index,
env->pc, env->regs[0], env->sregs[PS], env->sregs[CCOUNT]);
if (env->config->exception_vector[env->exception_index]) {
env->pc = relocated_vector(env,
env->config->exception_vector[env->exception_index]);
env->exception_taken = 1;
} else {
qemu_log("%s(pc = %08x) bad exception_index: %d\n",
__func__, env->pc, env->exception_index);
}
break;
case EXC_IRQ:
break;
default:
qemu_log("%s(pc = %08x) unknown exception_index: %d\n",
__func__, env->pc, env->exception_index);
break;
}
check_interrupts(env);
}
void lr35902_cpu_device::execute_run()
{
do
{
if (m_dma_cycles_to_burn > 0)
{
if (m_dma_cycles_to_burn < 4)
{
cycles_passed(m_dma_cycles_to_burn);
m_dma_cycles_to_burn = 0;
}
else
{
cycles_passed(4);
m_dma_cycles_to_burn -= 4;
}
}
else
{
if ( m_execution_state ) {
uint8_t x;
/* Execute instruction */
switch( m_op ) {
#include "opc_main.hxx"
default:
// actually this should lock up the cpu!
logerror("LR35902: Illegal opcode $%02X @ %04X\n", m_op, m_PC);
break;
}
} else {
/* Fetch and count cycles */
bool was_halted = (m_enable & HALTED);
check_interrupts();
debugger_instruction_hook(m_PC);
if ( m_enable & HALTED ) {
cycles_passed(m_has_halt_bug ? 2 : 4);
m_execution_state = 1;
m_entering_halt = false;
} else {
if (was_halted) {
m_PC++;
} else {
m_op = mem_read_byte( m_PC++ );
}
}
}
m_execution_state ^= 1;
}
} while (m_icount > 0);
}
WRITE8_DEVICE_HANDLER_TRAMPOLINE(acia6850, acia6850_data_w)
{
if (LOG) logerror("MC6850 '%s' Data: %02x\n", tag(), data);
if (!m_reset)
{
m_tdr = data;
m_status &= ~ACIA6850_STATUS_TDRE;
check_interrupts();
}
else
{
logerror("%s:ACIA %p: Data write while in reset!\n", m_machine.describe_context(), this);
}
}
static void xtensa_set_irq(void *opaque, int irq, int active)
{
CPUXtensaState *env = opaque;
if (irq >= env->config->ninterrupt) {
qemu_log("%s: bad IRQ %d\n", __func__, irq);
} else {
uint32_t irq_bit = 1 << irq;
if (active) {
env->sregs[INTSET] |= irq_bit;
} else if (env->config->interrupt[irq].inttype == INTTYPE_LEVEL) {
env->sregs[INTSET] &= ~irq_bit;
}
check_interrupts(env);
}
}
INPUT_PORTS_END
//**************************************************************************
// DEVICE CONFIGURATION
//**************************************************************************
//-------------------------------------------------
// vic2_interface vic_intf
//-------------------------------------------------
WRITE_LINE_MEMBER( vic10_state::vic_irq_w )
{
m_vic_irq = state;
check_interrupts();
}
void tms32082_mp_device::execute_run()
{
while (m_icount > 0)
{
m_pc = m_fetchpc;
check_interrupts();
debugger_instruction_hook(this, m_pc);
m_ir = fetch();
execute();
m_icount--;
};
return;
}
//-------------------------------------------------
// z80daisy_irq_reti - return from interrupt
//-------------------------------------------------
void z80sio_device::z80daisy_irq_reti()
{
int i;
LOGINT("%s %s \n",FUNCNAME, tag());
// loop over all interrupt sources
for (i = 0; i < 8; i++)
{
// find the first channel with an IEO pending
if (m_int_state[i] & Z80_DAISY_IEO)
{
// clear the IEO state and update the IRQs
m_int_state[i] &= ~Z80_DAISY_IEO;
check_interrupts();
return;
}
}
//logerror("z80sio_irq_reti: failed to find an interrupt to clear IEO on!\n");
}
void acia6850_device::check_dcd_input()
{
if (m_dcd)
{
// IRQ from DCD is edge triggered
if ( ! ( m_status & ACIA6850_STATUS_DCD ) )
{
m_status |= ACIA6850_STATUS_DCD;
m_dcd_triggered = true;
// Asserting DCD clears RDRF
m_status &= ~ACIA6850_STATUS_RDRF;
check_interrupts();
}
}
else if ((m_status & (ACIA6850_STATUS_DCD | ACIA6850_STATUS_IRQ)) == ACIA6850_STATUS_DCD)
{
m_status &= ~ACIA6850_STATUS_DCD;
}
}
void acia6850_device::rx_clock_in()
{
int dcd = m_in_dcd_func();
if (dcd)
{
m_status |= ACIA6850_STATUS_DCD;
check_interrupts();
}
else if ((m_status & (ACIA6850_STATUS_DCD|ACIA6850_STATUS_IRQ)) == ACIA6850_STATUS_DCD)
{
m_status &= ~ACIA6850_STATUS_DCD;
}
m_rx_counter ++;
if ( m_rx_counter > m_divide - 1)
{
rx_tick();
m_rx_counter = 0;
}
}
void z80dart_device::trigger_interrupt(int index, int state)
{
UINT8 vector = m_chanB->m_wr[2];
int priority = (index << 2) | state;
LOG(("Z80DART \"%s\" Channel %c : Interrupt Request %u\n", tag(), 'A' + index, state));
if ((index == CHANNEL_B) && (m_chanB->m_wr[1] & z80dart_channel::WR1_STATUS_VECTOR))
{
// status affects vector
vector = (m_chanB->m_wr[2] & 0xf1) | (!index << 3) | (state << 1);
}
// update vector register
m_chanB->m_rr[2] = vector;
// trigger interrupt
m_int_state[priority] |= Z80_DAISY_INT;
m_chanA->m_rr[0] |= z80dart_channel::RR0_INTERRUPT_PENDING;
// check for interrupt
check_interrupts();
}
static TIMER_CALLBACK(dmac_dma_proc)
{
amiga_state *state = machine.driver_data<amiga_state>();
while( dmac_data.wtc > 0 )
{
UINT16 dat16;
UINT8 dat8;
if ( matsucd_get_next_byte( &dat8 ) < 0 )
break;
dat16 = dat8;
if ( matsucd_get_next_byte( &dat8 ) < 0 )
break;
dat16 <<= 8;
dat16 |= dat8;
(*state->m_chip_ram_w)(state, dmac_data.acr, dat16);
dmac_data.acr += 2;
dmac_data.wtc--;
}
if ( dmac_data.wtc > 0 )
{
matsucd_read_next_block();
dmac_data.dma_timer->adjust(attotime::from_msec( CD_SECTOR_TIME ));
}
else
{
dmac_data.istr |= ISTR_INT_P | ISTR_E_INT;
check_interrupts( machine );
}
}
//-------------------------------------------------
// trigger_interrupt - TODO: needs attention for SIO
//-------------------------------------------------
void z80sio_device::trigger_interrupt(int index, int state)
{
uint8_t vector = m_chanB->m_wr2;
int priority;
LOGINT("%s %s \n",FUNCNAME, tag());
#if 0
if((m_variant == TYPE_I8274) || (m_variant == TYPE_UPD7201))
{
int prio_level = 0;
switch(state)
{
case z80sio_channel::INT_TRANSMIT:
prio_level = 1;
break;
case z80sio_channel::INT_RECEIVE:
case z80sio_channel::INT_SPECIAL:
prio_level = 0;
break;
case z80sio_channel::INT_EXTERNAL:
prio_level = 2;
break;
}
if(m_chanA->m_wr2 & z80sio_channel::WR2_PRIORITY)
{
priority = (prio_level * 2) + index;
}
else
{
priority = (prio_level == 2) ? index + 4 : ((index * 2) + prio_level);
}
if (m_chanB->m_wr1 & z80sio_channel::WR1_STATUS_VECTOR)
{
vector = (!index << 2) | state;
if((m_chanA->m_wr1 & 0x18) == z80sio_channel::WR2_MODE_8086_8088)
{
vector = (m_chanB->m_wr2 & 0xf8) | vector;
}
else
{
vector = (m_chanB->m_wr2 & 0xe3) | (vector << 2);
}
}
}
else
{
#endif
priority = (index << 2) | state;
if (m_chanB->m_wr1 & z80sio_channel::WR1_STATUS_VECTOR)
{
// status affects vector
vector = (m_chanB->m_wr2 & 0xf1) | (!index << 3) | (state << 1);
}
// }
// update vector register
m_chanB->m_rr2 = vector;
// trigger interrupt
m_int_state[priority] |= Z80_DAISY_INT;
m_chanA->m_rr0 |= z80sio_channel::RR0_INTERRUPT_PENDING;
// check for interrupt
check_interrupts();
}
//-------------------------------------------------
// m1_r - interrupt acknowledge
//-------------------------------------------------
int z80sio_device::m1_r()
{
LOGINT("%s %s \n",FUNCNAME, tag());
return z80daisy_irq_ack();
}
