示例#1
0
/*******************************************************************************
 * put_ep93xx_uart
 * 
 * Send a character out the debug_device[0] UART
 * 
 * Note that we wait for TXFF (Transmit Fifo Full) condition to clear to indicate
 * that we can write a character as this will work whether the transmit fifo is
 * enabled or not where as TXFE and BUSY will cause unneccesary delays when the
 * fifo is enabled
*/
void put_ep93xx_uart(int c)
{
	paddr_t base = dbg_device[0].base;

	ASSERT(base != NULL);

	chip_access(base, 0, 1, EP93xx_UART1_SIZE);
	while (chip_read32(EP93xx_UART_FLAGS) & EP93xx_UART_FLAGS_TXFF);
	chip_write32(EP93xx_UART_DATA, (unsigned)c & 0xFFU);
	chip_done();
}
unsigned long
rtc_time_omap(unsigned base)
{
	struct tm	tm;

	hwi_add_device(HWI_ITEM_BUS_UNKNOWN, HWI_ITEM_DEVCLASS_RTC, "omap", 0);
	hwi_add_location(base, OMAP_RTC_SIZE, 0, hwi_find_as(base, 1));

	// get the current time from the RTC, and convert it to seconds since epoch

    chip_access(base, 0, 0, OMAP_RTC_SIZE);

	// start the RTC, if it's not already running
	chip_write32(OMAP_RTC_CTRL, 0x01);

    // convert BCD to binary
    tm.tm_sec  = bcd2bin(chip_read32(OMAP_RTC_SECONDS) & 0xff);    // seconds
    tm.tm_min  = bcd2bin(chip_read32(OMAP_RTC_MINUTES) & 0xff);    // minutes
    tm.tm_hour = bcd2bin(chip_read32(OMAP_RTC_HOURS) & 0xff);   // hours
    tm.tm_mday = bcd2bin(chip_read32(OMAP_RTC_DAYS) & 0xff);    // day
    tm.tm_mon  = bcd2bin(chip_read32(OMAP_RTC_MONTHS) & 0xff);    // month
    tm.tm_year = (bcd2bin(chip_read32(OMAP_RTC_YEARS) & 0xff))+100;   // year

    chip_done();

    return(calc_time_t(&tm));

}
示例#3
0
/*******************************************************************************
 * init_ep93xx_uart
 * 
 * Initialise UART <channel>
 * 
 * note that updates to the LNCTRL registers MUST occur as 8 bit writes to
 * the LOW, MID and finally the HIGH register. This is true even if the
 * HIGH register value will not change (ie. you must read it out then write
 * it back).
 * The Low and Mid registers hold the LSB and MSB of the baudrate divisor.
 * 
 * The baud rate divisor is caclulated as follows (pg 14-21 of EP93xx Users Guide)
 * 		
 * 		BAUDDIV = (FUARTCLK / 16 * Baud rate)) – 1
 * 
*/
void init_ep93xx_uart(unsigned channel, const char *init, const char *defaults)
{
	unsigned baud = 0;
	unsigned clk = 0;
	uint16_t baudrate_div;
	const unsigned long fuart_clk = ep93xx_get_uartclk();
	
	/* get the baud rate from the defaults string */
	parse_line(channel, defaults, &baud, &clk);
	ASSERT(baud != 0);

	/* we don't require the 'clk' option but if its passed it must agree with get_fuartclk() */
	ASSERT((clk == 0) || (clk == fuart_clk));

	/* startup expects UART1 and UART2 for the debug devices (we don't care which is which) */
	ASSERT((dbg_device[channel].base == EP93xx_UART1_BASE) || (dbg_device[channel].base == EP93xx_UART2_BASE));

	chip_access(dbg_device[channel].base, 0, 1, EP93xx_UART1_SIZE);

	/* disable the UART */
	chip_write32(EP93xx_UART_CTRL, 0);

	/* figure out the baudrate divisor needed for the selected baud rate */
	baudrate_div = (fuart_clk / (16 * baud)) - 1;
	ASSERT(baudrate_div != 0);	// UART won't work if this is the case
	chip_write32(EP93xx_UART_LNCTRL_L, baudrate_div & 0xFFU);
	chip_write32(EP93xx_UART_LNCTRL_M, baudrate_div >> 8);

	/* select 8bit, no-parity, 1 stop bit and no FIFO */
	chip_write32(EP93xx_UART_LNCTRL_H, EP93xx_UART_LNCTRL_H_8N1);

	/* clear any pending interrupts (just in case) */
	chip_write32(EP93xx_UART_INTR, 0);

	/* Enable UART (no interrupts) */
	chip_write32(EP93xx_UART_CTRL, EP93xx_UART_CTRL_ENABLE);

	chip_done();
	
	/* make sure the UART is enabled in the EP93xx_SYSCTRL_DEVICECFG register */
	{
		uint32_t enable_mask = (dbg_device[channel].base == EP93xx_UART1_BASE) ? 0x00040000U : 0x00100000U;
		chip_access(EP93xx_SYSCTRL_BASE, 0, 1, EP93xx_SYSCTRL_SIZE);
		chip_write32(EP93xx_SYSCTRL_DEVICECFG, chip_read32(EP93xx_SYSCTRL_DEVICECFG) | enable_mask);
		chip_done();
	}
}