示例#1
0
/* Entry from the mainboard. */
void romstage_common(struct romstage_params *params)
{
	struct romstage_handoff *handoff;
	struct chipset_power_state *ps;
	int prev_sleep_state;

	timestamp_add_now(TS_BEFORE_INITRAM);

	ps = fill_power_state();
	prev_sleep_state = chipset_prev_sleep_state(ps);

	printk(BIOS_DEBUG, "prev_sleep_state = S%d\n", prev_sleep_state);

#if CONFIG_ELOG_BOOT_COUNT
	if (prev_sleep_state != 3)
		boot_count_increment();
#endif


	/* Initialize RAM */
	raminit(params->mrc_params, prev_sleep_state);

	timestamp_add_now(TS_AFTER_INITRAM);

	handoff = romstage_handoff_find_or_add();
	if (handoff != NULL)
		handoff->s3_resume = (prev_sleep_state == 3);
	else
		printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");

	if (CONFIG_LPC_TPM) {
		init_tpm(prev_sleep_state == 3);
	}
}
示例#2
0
/* Entry from the mainboard. */
void romstage_common(struct romstage_params *params)
{
	struct chipset_power_state *ps;
	int prev_sleep_state;

	timestamp_add_now(TS_BEFORE_INITRAM);

	ps = fill_power_state();
	prev_sleep_state = chipset_prev_sleep_state(ps);

	printk(BIOS_DEBUG, "prev_sleep_state = S%d\n", prev_sleep_state);

#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)
	if (prev_sleep_state != ACPI_S3)
		boot_count_increment();
#endif


	/* Initialize RAM */
	raminit(params->mrc_params, prev_sleep_state);

	timestamp_add_now(TS_AFTER_INITRAM);

	romstage_handoff_init(prev_sleep_state == ACPI_S3);
}
示例#3
0
/* returns prev_sleep_state */
int fill_power_state(struct chipset_power_state *ps)
{
	int i;
	uintptr_t pmc_bar0 = read_pmc_mmio_bar();

	ps->pm1_sts = inw(ACPI_PMIO_BASE + PM1_STS);
	ps->pm1_en = inw(ACPI_PMIO_BASE + PM1_EN);
	ps->pm1_cnt = inl(ACPI_PMIO_BASE + PM1_CNT);
	ps->tco_sts = inl(ACPI_PMIO_BASE + TCO_STS);
	ps->prsts = read32((void *)(pmc_bar0 + PRSTS));
	ps->gen_pmcon1 =read32((void *)(pmc_bar0 + GEN_PMCON1));
	ps->gen_pmcon2 = read32((void *)(pmc_bar0 + GEN_PMCON2));
	ps->gen_pmcon3 = read32((void *)(pmc_bar0 + GEN_PMCON3));

	ps->prev_sleep_state = chipset_prev_sleep_state(ps);

	printk(BIOS_DEBUG, "pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n",
		ps->pm1_sts, ps->pm1_en, ps->pm1_cnt);
	printk(BIOS_DEBUG, "prsts: %08x tco_sts: %08x\n",
		ps->prsts, ps->tco_sts);
	printk(BIOS_DEBUG,
		 "gen_pmcon1: %08x gen_pmcon2: %08x gen_pmcon3: %08x\n",
		ps->gen_pmcon1, ps->gen_pmcon2, ps->gen_pmcon3);
	printk(BIOS_DEBUG, "smi_en: %08x smi_sts: %08x\n",
		inl(ACPI_PMIO_BASE + SMI_EN), inl(ACPI_PMIO_BASE + SMI_STS));
	for (i=0; i < GPE0_REG_MAX; i++) {
		ps->gpe0_sts[i] = inl(ACPI_PMIO_BASE + GPE0_STS(i));
		ps->gpe0_en[i] = inl(ACPI_PMIO_BASE + GPE0_EN(i));
		printk(BIOS_DEBUG, "gpe0_sts[%d]: %08x gpe0_en[%d]: %08x\n",
			i, ps->gpe0_sts[i], i, ps->gpe0_en[i]);
	}
	printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state);
	return ps->prev_sleep_state;
}
示例#4
0
int arch_fsp_init(void)
{
	void *nvs;
	int stack = CONFIG_FSP_TEMP_RAM_ADDR;
	int boot_mode = BOOT_FULL_CONFIG;
#ifdef CONFIG_HAVE_ACPI_RESUME
	int prev_sleep_state = chipset_prev_sleep_state();
	gd->arch.prev_sleep_state = prev_sleep_state;
#endif

	if (!gd->arch.hob_list) {
#ifdef CONFIG_ENABLE_MRC_CACHE
		nvs = fsp_prepare_mrc_cache();
#else
		nvs = NULL;
#endif

#ifdef CONFIG_HAVE_ACPI_RESUME
		if (prev_sleep_state == ACPI_S3) {
			if (nvs == NULL) {
				/* If waking from S3 and no cache then */
				debug("No MRC cache found in S3 resume path\n");
				post_code(POST_RESUME_FAILURE);
				/* Clear Sleep Type */
				chipset_clear_sleep_state();
				/* Reboot */
				debug("Rebooting..\n");
				outb(SYS_RST | RST_CPU, IO_PORT_RESET);
				/* Should not reach here.. */
				panic("Reboot System");
			}

			/*
			 * DM is not avaiable yet at this point, hence call
			 * CMOS access library which does not depend on DM.
			 */
			stack = cmos_read32(CMOS_FSP_STACK_ADDR);
			boot_mode = BOOT_ON_S3_RESUME;
		}
#endif
		/*
		 * The first time we enter here, call fsp_init().
		 * Note the execution does not return to this function,
		 * instead it jumps to fsp_continue().
		 */
		fsp_init(stack, boot_mode, nvs);
	} else {
		/*
		 * The second time we enter here, adjust the size of malloc()
		 * pool before relocation. Given gd->malloc_base was adjusted
		 * after the call to board_init_f_init_reserve() in arch/x86/
		 * cpu/start.S, we should fix up gd->malloc_limit here.
		 */
		gd->malloc_limit += CONFIG_FSP_SYS_MALLOC_F_LEN;
	}

	return 0;
}
示例#5
0
/*******************************************************************************
 * The FSP early_init function returns to this function.
 * Memory is setup and the stack is set by the FSP.
 */
void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
	int cbmem_was_initted;
	void *cbmem_hob_ptr;
	uint32_t prev_sleep_state;
	struct romstage_handoff *handoff;

	timestamp_add_now(TS_AFTER_INITRAM);

	post_code(0x4a);
	printk(BIOS_DEBUG, "%s status: %x  hob_list_ptr: %x\n",
		__func__, (u32) status, (u32) hob_list_ptr);

#if IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE)
	/* FSP reconfigures USB, so reinit it to have debug */
	usbdebug_init();
#endif	/* IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE) */

	printk(BIOS_DEBUG, "FSP Status: 0x%0x\n", (u32)status);

	/* Get previous sleep state again and clear */
	prev_sleep_state = chipset_prev_sleep_state(1);
	printk(BIOS_DEBUG, "%s: prev_sleep_state = S%d\n", __func__, prev_sleep_state);

	report_platform_info();

	post_code(0x4b);

	late_mainboard_romstage_entry();
	post_code(0x4c);

	/* if S3 resume skip ram check */
	if (prev_sleep_state != 3) {
		quick_ram_check();
		post_code(0x4d);
	}

	cbmem_was_initted = !cbmem_recovery(prev_sleep_state == 3);

	/* Save the HOB pointer in CBMEM to be used in ramstage*/
	cbmem_hob_ptr = cbmem_add (CBMEM_ID_HOB_POINTER, sizeof(*hob_list_ptr));
	*(u32*)cbmem_hob_ptr = (u32)hob_list_ptr;
	post_code(0x4e);

	handoff = romstage_handoff_find_or_add();
	if (handoff != NULL)
		handoff->s3_resume = (prev_sleep_state == 3);
	else
		printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");

	post_code(0x4f);

	/* Load the ramstage. */
	copy_and_run();
	while (1);
}
/* Set up the Baytrail specific structures for the call into the FSP */
void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams,
		FSP_INFO_HEADER *fsp_ptr)
{
	FSP_INIT_RT_BUFFER *pFspRtBuffer = pFspInitParams->RtBufferPtr;
	uint32_t prev_sleep_state;

	/* Get previous sleep state but don't clear */
	prev_sleep_state = chipset_prev_sleep_state(0);
	printk(BIOS_INFO, "prev_sleep_state = S%d\n", prev_sleep_state);

	/* Initialize the UPD Data */
	GetUpdDefaultFromFsp (fsp_ptr, pFspRtBuffer->Common.UpdDataRgnPtr);
	ConfigureDefaultUpdData(fsp_ptr, pFspRtBuffer->Common.UpdDataRgnPtr);
	pFspInitParams->NvsBufferPtr = NULL;

#if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)
	/* Find the fastboot cache that was saved in the ROM */
	pFspInitParams->NvsBufferPtr = find_and_set_fastboot_cache();
#endif

	if (prev_sleep_state == 3) {
		/* S3 resume */
		if ( pFspInitParams->NvsBufferPtr == NULL) {
			/* If waking from S3 and no cache then. */
			printk(BIOS_WARNING, "No MRC cache found in S3 resume path.\n");
			post_code(POST_RESUME_FAILURE);
			/* Clear Sleep Type */
			outl(inl(ACPI_BASE_ADDRESS + PM1_CNT) &
				~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT);
			/* Reboot */
			printk(BIOS_WARNING,"Rebooting..\n" );
			warm_reset();
			/* Should not reach here.. */
			die("Reboot System\n");
		}
		pFspRtBuffer->Common.BootMode = BOOT_ON_S3_RESUME;
	} else {
		/* Not S3 resume */
		pFspRtBuffer->Common.BootMode = BOOT_WITH_FULL_CONFIGURATION;
	}

	return;
}
示例#7
0
void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd)
{
	const struct mrc_saved_data *mrc_cache;
	struct FSPM_ARCH_UPD *arch_upd = &mupd->FspmArchUpd;
	struct chipset_power_state *ps = car_get_var_ptr(&power_state);
	int prev_sleep_state = chipset_prev_sleep_state(ps);

	fill_console_params(mupd);
	mainboard_memory_init_params(mupd);

	/* Do NOT let FSP do any GPIO pad configuration */
	mupd->FspmConfig.PreMemGpioTablePtr = (uintptr_t) NULL;
	/* Reserve enough memory under TOLUD to save CBMEM header */
	mupd->FspmArchUpd.BootLoaderTolumSize = cbmem_overhead_size();
	/*
	 * FSPM_UPD passed here is populated with default values provided by
	 * the blob itself. We let FSPM use top of CAR region of the size it
	 * requests.
	 * TODO: add checks to avoid overlap/conflict of CAR usage.
	 */
	mupd->FspmArchUpd.StackBase = _car_region_end -
					mupd->FspmArchUpd.StackSize;

	arch_upd->BootMode = FSP_BOOT_WITH_FULL_CONFIGURATION;

	if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS)) {
		if (!mrc_cache_get_current_with_version(&mrc_cache, 0)) {
			/* MRC cache found */
			arch_upd->NvsBufferPtr = (void *)mrc_cache->data;
			arch_upd->BootMode =
				prev_sleep_state == SLEEP_STATE_S3 ?
				FSP_BOOT_ON_S3_RESUME:
				FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES;
			printk(BIOS_DEBUG, "MRC cache found, size %x bootmode:%d\n",
						mrc_cache->size, arch_upd->BootMode);
		} else
			printk(BIOS_DEBUG, "MRC cache was not found\n");
	}
}