示例#1
0
/**
 * davinci_spi_setup_transfer - This functions will determine transfer method
 * @spi: spi device on which data transfer to be done
 * @t: spi transfer in which transfer info is filled
 *
 * This function determines data transfer method (8/16/32 bit transfer).
 * It will also set the SPI Clock Control register according to
 * SPI slave device freq.
 */
static int davinci_spi_setup_transfer(struct spi_device *spi,
		struct spi_transfer *t)
{

	struct davinci_spi *davinci_spi;
	struct davinci_spi_platform_data *pdata;
	u8 bits_per_word = 0;
	u32 hz = 0, prescale = 0, clkspeed;

	davinci_spi = spi_master_get_devdata(spi->master);
	pdata = davinci_spi->pdata;

	if (t) {
		bits_per_word = t->bits_per_word;
		hz = t->speed_hz;
	}

	/* if bits_per_word is not set then set it default */
	if (!bits_per_word)
		bits_per_word = spi->bits_per_word;

	/*
	 * Assign function pointer to appropriate transfer method
	 * 8bit, 16bit or 32bit transfer
	 */
	if (bits_per_word <= 8 && bits_per_word >= 2) {
		davinci_spi->get_rx = davinci_spi_rx_buf_u8;
		davinci_spi->get_tx = davinci_spi_tx_buf_u8;
		davinci_spi->slave[spi->chip_select].bytes_per_word = 1;
	} else if (bits_per_word <= 16 && bits_per_word >= 2) {
		davinci_spi->get_rx = davinci_spi_rx_buf_u16;
		davinci_spi->get_tx = davinci_spi_tx_buf_u16;
		davinci_spi->slave[spi->chip_select].bytes_per_word = 2;
	} else
		return -EINVAL;

	if (!hz)
		hz = spi->max_speed_hz;

	clear_fmt_bits(davinci_spi->base, SPIFMT_CHARLEN_MASK,
			spi->chip_select);
	set_fmt_bits(davinci_spi->base, bits_per_word & 0x1f,
			spi->chip_select);

	clkspeed = clk_get_rate(davinci_spi->clk);
	if (hz > clkspeed / 2)
		prescale = 1 << 8;
	if (hz < clkspeed / 256)
		prescale = 255 << 8;
	if (!prescale)
		prescale = ((clkspeed / hz - 1) << 8) & 0x0000ff00;

	clear_fmt_bits(davinci_spi->base, 0x0000ff00, spi->chip_select);
	set_fmt_bits(davinci_spi->base, prescale, spi->chip_select);

	return 0;
}
示例#2
0
static int davinci_spi_bufs_prep(struct spi_device *spi,
				 struct davinci_spi *davinci_spi,
				 struct davinci_spi_config_t *spi_cfg)
{
	u32 sPIPC0;

	/* configuraton parameter for SPI */
	if (spi_cfg->lsb_first)
		set_fmt_bits(davinci_spi->base, SPI_SPIFMT_SHIFTDIR_MASK);
	else
		clear_fmt_bits(davinci_spi->base, SPI_SPIFMT_SHIFTDIR_MASK);

	if (spi_cfg->clk_high)
		set_fmt_bits(davinci_spi->base, SPI_SPIFMT_POLARITY_MASK);
	else
		clear_fmt_bits(davinci_spi->base, SPI_SPIFMT_POLARITY_MASK);

	if (spi_cfg->phase_in)
		set_fmt_bits(davinci_spi->base, SPI_SPIFMT_PHASE_MASK);
	else
		clear_fmt_bits(davinci_spi->base, SPI_SPIFMT_PHASE_MASK);

	if (davinci_spi->version == DAVINCI_SPI_VERSION_2) {
		clear_fmt_bits(davinci_spi->base, SPI_SPIFMT_WDELAY_MASK);
		set_fmt_bits(davinci_spi->base,
				((spi_cfg->wdelay << SPI_SPIFMT_WDELAY_SHIFT)
					 & SPI_SPIFMT_WDELAY_MASK));

		if (spi_cfg->odd_parity)
			set_fmt_bits(davinci_spi->base,
					SPI_SPIFMT_ODD_PARITY_MASK);
		else
			clear_fmt_bits(davinci_spi->base,
					SPI_SPIFMT_ODD_PARITY_MASK);

		if (spi_cfg->parity_enable)
			set_fmt_bits(davinci_spi->base,
					SPI_SPIFMT_PARITYENA_MASK);
		else
			clear_fmt_bits(davinci_spi->base,
					SPI_SPIFMT_PARITYENA_MASK);

		if (spi_cfg->wait_enable)
			set_fmt_bits(davinci_spi->base,
					SPI_SPIFMT_WAITENA_MASK);
		else
			clear_fmt_bits(davinci_spi->base,
					SPI_SPIFMT_WAITENA_MASK);

		if (spi_cfg->timer_disable)
			set_fmt_bits(davinci_spi->base,
					SPI_SPIFMT_DISTIMER_MASK);
		else
			clear_fmt_bits(davinci_spi->base,
					SPI_SPIFMT_DISTIMER_MASK);
	}

	/* Clock internal */
	if (spi_cfg->clk_internal)
		set_bits(davinci_spi->base + SPIGCR1, SPI_SPIGCR1_CLKMOD_MASK);
	else
		clear_bits(davinci_spi->base + SPIGCR1,
				SPI_SPIGCR1_CLKMOD_MASK);

	/* master mode default */
	set_bits(davinci_spi->base + SPIGCR1, SPI_SPIGCR1_MASTER_MASK);

	if (spi_cfg->intr_level)
		iowrite32(SPI_INTLVL_1, davinci_spi->base + SPILVL);
	else
		iowrite32(SPI_INTLVL_0, davinci_spi->base + SPILVL);

	switch (spi_cfg->pin_op_modes) {
	case SPI_OPMODE_3PIN:
		sPIPC0 = (SPI_SPIPC0_DIFUN_DI << SPI_SPIPC0_DIFUN_SHIFT)
			| (SPI_SPIPC0_DOFUN_DO << SPI_SPIPC0_DOFUN_SHIFT)
			| (SPI_SPIPC0_CLKFUN_CLK << SPI_SPIPC0_CLKFUN_SHIFT);
		break;

	case SPI_OPMODE_SPISCS_4PIN:
		sPIPC0 = (SPI_SPIPC0_DIFUN_DI << SPI_SPIPC0_DIFUN_SHIFT)
			| (SPI_SPIPC0_DOFUN_DO << SPI_SPIPC0_DOFUN_SHIFT)
			| (SPI_SPIPC0_CLKFUN_CLK << SPI_SPIPC0_CLKFUN_SHIFT)
			| (1 << spi->chip_select);
		break;

	case SPI_OPMODE_SPIENA_4PIN:
		sPIPC0 = (SPI_SPIPC0_DIFUN_DI << SPI_SPIPC0_DIFUN_SHIFT)
			| (SPI_SPIPC0_DOFUN_DO << SPI_SPIPC0_DOFUN_SHIFT)
			| (SPI_SPIPC0_CLKFUN_CLK << SPI_SPIPC0_CLKFUN_SHIFT)
			| (SPI_SPIPC0_SPIENA << SPI_SPIPC0_SPIENA_SHIFT);
		break;

	case SPI_OPMODE_5PIN:
		sPIPC0 = (SPI_SPIPC0_DIFUN_DI << SPI_SPIPC0_DIFUN_SHIFT)
			| (SPI_SPIPC0_DOFUN_DO << SPI_SPIPC0_DOFUN_SHIFT)
			| (SPI_SPIPC0_CLKFUN_CLK << SPI_SPIPC0_CLKFUN_SHIFT)
			| (SPI_SPIPC0_SPIENA << SPI_SPIPC0_SPIENA_SHIFT)
			| (1 << spi->chip_select);
		break;

	default:
		return -1;
	}

	iowrite32(sPIPC0, davinci_spi->base + SPIPC0);

	if (spi_cfg->loop_back)
		set_bits(davinci_spi->base + SPIGCR1,
				SPI_SPIGCR1_LOOPBACK_MASK);
	else
		clear_bits(davinci_spi->base + SPIGCR1,
				SPI_SPIGCR1_LOOPBACK_MASK);

	return 0;
}
示例#3
0
/**
 * davinci_spi_setup_transfer - This functions will determine transfer method
 * @spi: spi device on which data transfer to be done
 * @t: spi transfer in which transfer info is filled
 *
 * This function determines data transfer method (8/16/32 bit transfer).
 * It will also set the SPI Clock Control register according to
 * SPI slave device freq.
 */
static int davinci_spi_setup_transfer(struct spi_device *spi,
		struct spi_transfer *t)
{

	struct davinci_spi *davinci_spi;
	struct davinci_spi_platform_data *pdata;
	u8 bits_per_word = 0;
	u32 hz = 0, prescale;

	davinci_spi = spi_master_get_devdata(spi->master);
	pdata = davinci_spi->pdata;

	if (t) {
		bits_per_word = t->bits_per_word;
		hz = t->speed_hz;
	}

	/* if bits_per_word is not set then set it default */
	if (!bits_per_word)
		bits_per_word = spi->bits_per_word;

	/* Assign function pointer to appropriate transfer method */
	/* 8bit/16bit or 32bit transfer */
	if (bits_per_word <= 8 && bits_per_word >= 2) {
		davinci_spi->get_rx = davinci_spi_rx_buf_u8;
		davinci_spi->get_tx = davinci_spi_tx_buf_u8;
		davinci_spi->slave[spi->chip_select].bytes_per_word = 1;
	} else if (bits_per_word <= 16 && bits_per_word >= 2) {
		davinci_spi->get_rx = davinci_spi_rx_buf_u16;
		davinci_spi->get_tx = davinci_spi_tx_buf_u16;
		davinci_spi->slave[spi->chip_select].bytes_per_word = 2;
	} else
		return -1;

	if (!hz) {
		hz = spi->max_speed_hz;
		if (!hz) {
			hz = 2000000;	/* defaulting to 2Mhz */
			pr_info("[SPI] -> Slave device speed not set "
				"correctly. Trying with %dHz\n", hz);
		}
	}

	if (hz <= 600000 || hz >= 50000000) {
		hz = 2000000;
		pr_err("[SPI] -> Slave device speed is out of range "
			"Speed should be between 600 Khz - 50 Mhz "
			"Trying with %dHz\n", hz);
	}

	clear_fmt_bits(davinci_spi->base, SPI_SPIFMT_CHARLEN_MASK);
	set_fmt_bits(davinci_spi->base, bits_per_word & 0x1f);

	prescale = (clk_get_rate(pdata->clk_info) + (hz / 2));
	prescale = ((prescale / hz) - 1) & 0xff;

	clear_fmt_bits(davinci_spi->base, 0x0000ff00);
	set_fmt_bits(davinci_spi->base, prescale << 8);

	return 0;
}
示例#4
0
static int davinci_spi_setup(struct spi_device *spi)
{
	int retval;
	struct davinci_spi *davinci_spi;
	struct davinci_spi_dma *davinci_spi_dma;
	struct device *sdev;

	davinci_spi = spi_master_get_devdata(spi->master);
	sdev = davinci_spi->bitbang.master->dev.parent;

	/* if bits per word length is zero then set it default 8 */
	if (!spi->bits_per_word)
		spi->bits_per_word = 8;

	davinci_spi->slave[spi->chip_select].cmd_to_write = 0;

	if (use_dma && davinci_spi->dma_channels) {
		davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];

		if ((davinci_spi_dma->dma_rx_channel == -1)
				|| (davinci_spi_dma->dma_tx_channel == -1)) {
			retval = davinci_spi_request_dma(spi);
			if (retval < 0)
				return retval;
		}
	}

	/*
	 * SPI in DaVinci and DA8xx operate between
	 * 600 KHz and 50 MHz
	 */
	if (spi->max_speed_hz < 600000 || spi->max_speed_hz > 50000000) {
		dev_dbg(sdev, "Operating frequency is not in acceptable "
				"range\n");
		return -EINVAL;
	}

	/*
	 * Set up SPIFMTn register, unique to this chipselect.
	 *
	 * NOTE: we could do all of these with one write.  Also, some
	 * of the "version 2" features are found in chips that don't
	 * support all of them...
	 */
	if (spi->mode & SPI_LSB_FIRST)
		set_fmt_bits(davinci_spi->base, SPIFMT_SHIFTDIR_MASK,
				spi->chip_select);
	else
		clear_fmt_bits(davinci_spi->base, SPIFMT_SHIFTDIR_MASK,
				spi->chip_select);

	if (spi->mode & SPI_CPOL)
		set_fmt_bits(davinci_spi->base, SPIFMT_POLARITY_MASK,
				spi->chip_select);
	else
		clear_fmt_bits(davinci_spi->base, SPIFMT_POLARITY_MASK,
				spi->chip_select);

	if (!(spi->mode & SPI_CPHA))
		set_fmt_bits(davinci_spi->base, SPIFMT_PHASE_MASK,
				spi->chip_select);
	else
		clear_fmt_bits(davinci_spi->base, SPIFMT_PHASE_MASK,
				spi->chip_select);

	/*
	 * Version 1 hardware supports two basic SPI modes:
	 *  - Standard SPI mode uses 4 pins, with chipselect
	 *  - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS)
	 *	(distinct from SPI_3WIRE, with just one data wire;
	 *	or similar variants without MOSI or without MISO)
	 *
	 * Version 2 hardware supports an optional handshaking signal,
	 * so it can support two more modes:
	 *  - 5 pin SPI variant is standard SPI plus SPI_READY
	 *  - 4 pin with enable is (SPI_READY | SPI_NO_CS)
	 */

	if (davinci_spi->version == SPI_VERSION_2) {
		clear_fmt_bits(davinci_spi->base, SPIFMT_WDELAY_MASK,
				spi->chip_select);
		set_fmt_bits(davinci_spi->base,
				(davinci_spi->pdata->wdelay
						<< SPIFMT_WDELAY_SHIFT)
					& SPIFMT_WDELAY_MASK,
				spi->chip_select);

		if (davinci_spi->pdata->odd_parity)
			set_fmt_bits(davinci_spi->base,
					SPIFMT_ODD_PARITY_MASK,
					spi->chip_select);
		else
			clear_fmt_bits(davinci_spi->base,
					SPIFMT_ODD_PARITY_MASK,
					spi->chip_select);

		if (davinci_spi->pdata->parity_enable)
			set_fmt_bits(davinci_spi->base,
					SPIFMT_PARITYENA_MASK,
					spi->chip_select);
		else
			clear_fmt_bits(davinci_spi->base,
					SPIFMT_PARITYENA_MASK,
					spi->chip_select);

		if (davinci_spi->pdata->wait_enable)
			set_fmt_bits(davinci_spi->base,
					SPIFMT_WAITENA_MASK,
					spi->chip_select);
		else
			clear_fmt_bits(davinci_spi->base,
					SPIFMT_WAITENA_MASK,
					spi->chip_select);

		if (davinci_spi->pdata->timer_disable)
			set_fmt_bits(davinci_spi->base,
					SPIFMT_DISTIMER_MASK,
					spi->chip_select);
		else
			clear_fmt_bits(davinci_spi->base,
					SPIFMT_DISTIMER_MASK,
					spi->chip_select);
	}

	retval = davinci_spi_setup_transfer(spi, NULL);

	return retval;
}