C++ (Cpp) clear_pm1_status示例

示例#1

文件： smi.c 项目： RafaelRMachado/Coreboot

void southbridge_smm_clear_state(void)
{
    u32 smi_en;

#if CONFIG_ELOG
    /* Log events from chipset before clearing */
    pch_log_state();
#endif
    printk(BIOS_DEBUG, "Initializing Southbridge SMI...");
    printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", get_pmbase());

    smi_en = inl(get_pmbase() + SMI_EN);
    if (smi_en & APMC_EN) {
        printk(BIOS_INFO, "SMI# handler already enabled?\n");
        return;
    }

    printk(BIOS_DEBUG, "\n");

    /* Dump and clear status registers */
    clear_smi_status();
    clear_pm1_status();
    clear_tco_status();
    clear_gpe_status();
}

示例#2

文件： smi.c 项目： RafaelRMachado/Coreboot

void southbridge_clear_smi_status(void)
{
	/* Clear SMI status */
	clear_smi_status();

	/* Clear PM1 status */
	clear_pm1_status();

	/* Set EOS bit so other SMIs can occur. */
	enable_smi(EOS);
}

示例#3

文件： smi.c 项目： lynxis/coreboot-signed

void southbridge_smm_clear_state(void)
{
	printk(BIOS_DEBUG, "Initializing Southbridge SMI...");

	if (get_smi_en() & APMC_EN) {
		printk(BIOS_INFO, "SMI# handler already enabled?\n");
		return;
	}

	printk(BIOS_DEBUG, "Done\n");

	/* Dump and clear status registers */
	clear_smi_status();
	clear_pm1_status();
	clear_tco_status();
	clear_gpe_status();
}

示例#4

文件： smi.c 项目： RafaelRMachado/Coreboot

void southbridge_smm_clear_state(void)
{
	u32 smi_en;

	printk(BIOS_DEBUG, "Initializing Southbridge SMI...");
	printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", ACPI_BASE_ADDRESS);

	smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN);
	if (smi_en & APMC_EN) {
		printk(BIOS_INFO, "SMI# handler already enabled?\n");
		return;
	}

	printk(BIOS_DEBUG, "\n");

	/* Dump and clear status registers */
	clear_smi_status();
	clear_pm1_status();
	clear_tco_status();
	clear_gpe_status();
}

示例#5

文件： smi.c 项目： andy737/firebrickRemote

void southbridge_smm_init(void)
{
	u32 smi_en;

#if CONFIG_ELOG
	/* Log events from chipset before clearing */
	pch_log_state();
#endif
	printk(BIOS_DEBUG, "Initializing Southbridge SMI...");
	printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", get_pmbase());

	smi_en = inl(get_pmbase() + SMI_EN);
	if (smi_en & APMC_EN) {
		printk(BIOS_INFO, "SMI# handler already enabled?\n");
		return;
	}

	printk(BIOS_DEBUG, "\n");

	/* Dump and clear status registers */
	clear_smi_status();
	clear_pm1_status();
	clear_tco_status();
	clear_gpe_status();

	/* Configure events */
	enable_pm1(PWRBTN_EN | GBL_EN);
	disable_gpe(PME_B0_EN);

	/* Enable SMI generation:
	 *  - on TCO events
	 *  - on APMC writes (io 0xb2)
	 *  - on writes to SLP_EN (sleep states)
	 *  - on writes to GBL_RLS (bios commands)
	 * No SMIs:
	 *  - on microcontroller writes (io 0x62/0x66)
	 */
	enable_smi(TCO_EN | APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS);
}

示例#6

void southcluster_smm_clear_state(void)
{
	uint32_t smi_en;

	/* Log events from chipset before clearing */
	southcluster_log_state();

	printk(BIOS_DEBUG, "Initializing Southbridge SMI...");
	printk(BIOS_SPEW, " pmbase = 0x%04x\n", get_pmbase());

	smi_en = inl(get_pmbase() + SMI_EN);
	if (smi_en & APMC_EN) {
		printk(BIOS_INFO, "SMI# handler already enabled?\n");
		return;
	}

	/* Dump and clear status registers */
	clear_smi_status();
	clear_pm1_status();
	clear_tco_status();
	clear_gpe_status();
	clear_alt_status();
	clear_pmc_status();
}