static int zynq_clock_probe(struct device_d *dev) { struct resource *iores; void __iomem *slcr_base; unsigned long ps_clk_rate = 33333330; iores = dev_request_mem_resource(dev, 0); if (IS_ERR(iores)) return PTR_ERR(iores); slcr_base = IOMEM(iores->start); clks[ps_clk] = clk_fixed("ps_clk", ps_clk_rate); clks[arm_pll] = zynq_pll_clk(ZYNQ_PLL_ARM, "arm_pll", slcr_base + 0x100); clks[ddr_pll] = zynq_pll_clk(ZYNQ_PLL_DDR, "ddr_pll", slcr_base + 0x104); clks[io_pll] = zynq_pll_clk(ZYNQ_PLL_IO, "io_pll", slcr_base + 0x108); clks[uart_clk] = zynq_periph_clk("uart_clk", slcr_base + 0x154); clks[uart0] = clk_gate("uart0", "uart_clk", slcr_base + 0x154, 0, 0, 0); clks[uart1] = clk_gate("uart1", "uart_clk", slcr_base + 0x154, 1, 0, 0); clks[gem0] = clk_gate("gem0", "io_pll", slcr_base + 0x140, 0, 0, 0); clks[gem1] = clk_gate("gem1", "io_pll", slcr_base + 0x144, 1, 0, 0); clks[cpu_clk] = zynq_cpu_clk("cpu_clk", slcr_base + 0x120); clks[cpu_6x4x] = zynq_cpu_subclk("cpu_6x4x", CPU_SUBCLK_6X4X, slcr_base + 0x120, slcr_base + 0x1C4); clks[cpu_3x2x] = zynq_cpu_subclk("cpu_3x2x", CPU_SUBCLK_3X2X, slcr_base + 0x120, slcr_base + 0x1C4); clks[cpu_2x] = zynq_cpu_subclk("cpu_2x", CPU_SUBCLK_2X, slcr_base + 0x120, slcr_base + 0x1C4); clks[cpu_1x] = zynq_cpu_subclk("cpu_1x", CPU_SUBCLK_1X, slcr_base + 0x120, slcr_base + 0x1C4); clk_register_clkdev(clks[cpu_3x2x], NULL, "arm_smp_twd"); clk_register_clkdev(clks[uart0], NULL, "zynq_serial0"); clk_register_clkdev(clks[uart1], NULL, "zynq_serial1"); clk_register_clkdev(clks[gem0], NULL, "macb0"); clk_register_clkdev(clks[gem1], NULL, "macb1"); clkdev_add_physbase(clks[cpu_3x2x], CORTEXA9_SCU_TIMER_BASE_ADDR, NULL); clkdev_add_physbase(clks[uart1], ZYNQ_UART1_BASE_ADDR, NULL); return 0; }
int mvebu_clk_gating_probe(struct device_d *dev) { struct device_node *np = dev->device_node; const struct of_device_id *match; const struct clk_gating_soc_desc *desc; struct clk_gating_ctrl *ctrl; struct gate *gate; struct clk *clk; void __iomem *base; const char *default_parent = NULL; int n; match = of_match_node(mvebu_clk_gating_ids, np); if (!match) return -EINVAL; desc = (const struct clk_gating_soc_desc *)match->data; base = dev_request_mem_region(dev, 0); if (!base) return -EINVAL; clk = of_clk_get(np, 0); if (IS_ERR(clk)) return -EINVAL; default_parent = clk->name; ctrl = xzalloc(sizeof(*ctrl)); /* Count, allocate, and register clock gates */ for (n = 0; desc[n].name;) n++; ctrl->num_gates = n; ctrl->gates = xzalloc(ctrl->num_gates * sizeof(*gate)); for (n = 0, gate = ctrl->gates; n < ctrl->num_gates; n++, gate++) { const char *parent = (desc[n].parent) ? desc[n].parent : default_parent; gate->bit_idx = desc[n].bit_idx; gate->clk = clk_gate(desc[n].name, parent, base, desc[n].bit_idx, 0, 0); WARN_ON(IS_ERR(gate->clk)); } return of_clk_add_provider(np, clk_gating_get_src, ctrl); }
int __init mx28_clocks_init(void __iomem *regs) { clks[ref_xtal] = clk_fixed("ref_xtal", 24000000); clks[pll0] = mxs_clk_pll("pll0", "ref_xtal", PLL0CTRL0, 17, 480000000); clks[pll1] = mxs_clk_pll("pll1", "ref_xtal", PLL1CTRL0, 17, 480000000); clks[pll2] = mxs_clk_pll("pll2", "ref_xtal", PLL2CTRL0, 23, 50000000); clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll0", FRAC0, 0); clks[ref_emi] = mxs_clk_ref("ref_emi", "pll0", FRAC0, 1); clks[ref_io1] = mxs_clk_ref("ref_io1", "pll0", FRAC0, 2); clks[ref_io0] = mxs_clk_ref("ref_io0", "pll0", FRAC0, 3); clks[ref_pix] = mxs_clk_ref("ref_pix", "pll0", FRAC1, 0); clks[ref_hsadc] = mxs_clk_ref("ref_hsadc", "pll0", FRAC1, 1); clks[ref_gpmi] = mxs_clk_ref("ref_gpmi", "pll0", FRAC1, 2); clks[gpmi_sel] = mxs_clk_mux("gpmi_sel", CLKSEQ, 2, 1, sel_gpmi, ARRAY_SIZE(sel_gpmi)); clks[ssp0_sel] = mxs_clk_mux("ssp0_sel", CLKSEQ, 3, 1, sel_io0, ARRAY_SIZE(sel_io0)); clks[ssp1_sel] = mxs_clk_mux("ssp1_sel", CLKSEQ, 4, 1, sel_io0, ARRAY_SIZE(sel_io0)); clks[ssp2_sel] = mxs_clk_mux("ssp2_sel", CLKSEQ, 5, 1, sel_io1, ARRAY_SIZE(sel_io1)); clks[ssp3_sel] = mxs_clk_mux("ssp3_sel", CLKSEQ, 6, 1, sel_io1, ARRAY_SIZE(sel_io1)); clks[emi_sel] = mxs_clk_mux("emi_sel", CLKSEQ, 7, 1, emi_sels, ARRAY_SIZE(emi_sels)); clks[etm_sel] = mxs_clk_mux("etm_sel", CLKSEQ, 8, 1, sel_cpu, ARRAY_SIZE(sel_cpu)); clks[lcdif_sel] = mxs_clk_mux("lcdif_sel", CLKSEQ, 14, 1, sel_pix, ARRAY_SIZE(sel_pix)); clks[cpu] = mxs_clk_mux("cpu", CLKSEQ, 18, 1, cpu_sels, ARRAY_SIZE(cpu_sels)); clks[ptp_sel] = mxs_clk_mux("ptp_sel", ENET, 19, 1, ptp_sels, ARRAY_SIZE(ptp_sels)); clks[cpu_pll] = mxs_clk_div("cpu_pll", "ref_cpu", CPU, 0, 6, 28); clks[cpu_xtal] = mxs_clk_div("cpu_xtal", "ref_xtal", CPU, 16, 10, 29); clks[hbus] = mxs_clk_div("hbus", "cpu", HBUS, 0, 5, 31); clks[xbus] = mxs_clk_div("xbus", "ref_xtal", XBUS, 0, 10, 31); clks[ssp0_gate] = mxs_clk_gate("ssp0_gate", "ssp0_sel", SSP0, 31); clks[ssp1_gate] = mxs_clk_gate("ssp1_gate", "ssp1_sel", SSP1, 31); clks[ssp2_gate] = mxs_clk_gate("ssp2_gate", "ssp2_sel", SSP2, 31); clks[ssp3_gate] = mxs_clk_gate("ssp3_gate", "ssp3_sel", SSP3, 31); clks[ssp0] = mxs_clk_div("ssp0", "ssp0_gate", SSP0, 0, 9, 29); clks[ssp1] = mxs_clk_div("ssp1", "ssp1_gate", SSP1, 0, 9, 29); clks[ssp2] = mxs_clk_div("ssp2", "ssp2_gate", SSP2, 0, 9, 29); clks[ssp3] = mxs_clk_div("ssp3", "ssp3_gate", SSP3, 0, 9, 29); clks[gpmi_div] = mxs_clk_div("gpmi_div", "gpmi_sel", GPMI, 0, 10, 29); clks[emi_pll] = mxs_clk_div("emi_pll", "ref_emi", EMI, 0, 6, 28); clks[emi_xtal] = mxs_clk_div("emi_xtal", "ref_xtal", EMI, 8, 4, 29); clks[lcdif_div] = mxs_clk_div("lcdif_div", "lcdif_sel", LCDIF, 0, 13, 29); clks[etm_div] = mxs_clk_div("etm_div", "etm_sel", ETM, 0, 7, 29); clks[clk32k_div] = mxs_clk_fixed_factor("clk32k_div", "ref_xtal", 1, 750); clks[rtc] = mxs_clk_fixed_factor("rtc", "ref_xtal", 1, 768); clks[lradc] = mxs_clk_fixed_factor("lradc", "clk32k", 1, 16); clks[clk32k] = mxs_clk_gate("clk32k", "clk32k_div", XTAL, 26); clks[pwm] = mxs_clk_gate("pwm", "ref_xtal", XTAL, 29); clks[uart] = mxs_clk_gate("uart", "ref_xtal", XTAL, 31); clks[gpmi] = mxs_clk_gate("gpmi", "gpmi_div", GPMI, 31); clks[emi] = mxs_clk_gate("emi", "emi_sel", EMI, 31); clks[lcdif] = mxs_clk_gate("lcdif", "lcdif_div", LCDIF, 31); clks[etm] = mxs_clk_gate("etm", "etm_div", ETM, 31); clks[fec_sleep] = mxs_clk_gate("fec_sleep", "hbus", ENET, 31); clks[fec] = mxs_clk_gate("fec", "fec_sleep", ENET, 30); clks[usb0_phy] = mxs_clk_gate("usb0_phy", "pll0", PLL0CTRL0, 18); clks[usb1_phy] = mxs_clk_gate("usb1_phy", "pll1", PLL1CTRL0, 18); clks[enet_out] = clk_gate("enet_out", "pll2", ENET, 18, 0, 0); clks[lcdif_comp] = mxs_clk_lcdif("lcdif_comp", clks[ref_pix], clks[lcdif_div], clks[lcdif]); clk_set_rate(clks[ref_io0], 480000000); clk_set_rate(clks[ref_io1], 480000000); clk_set_parent(clks[ssp0_sel], clks[ref_io0]); clk_set_parent(clks[ssp1_sel], clks[ref_io0]); clk_set_parent(clks[ssp2_sel], clks[ref_io1]); clk_set_parent(clks[ssp3_sel], clks[ref_io1]); clk_set_rate(clks[ssp0], 96000000); clk_set_rate(clks[ssp1], 96000000); clk_set_rate(clks[ssp2], 96000000); clk_set_rate(clks[ssp3], 96000000); clk_set_parent(clks[lcdif_sel], clks[ref_pix]); clk_enable(clks[enet_out]); clkdev_add_physbase(clks[ssp0], IMX_SSP0_BASE, NULL); clkdev_add_physbase(clks[ssp1], IMX_SSP1_BASE, NULL); clkdev_add_physbase(clks[ssp2], IMX_SSP2_BASE, NULL); clkdev_add_physbase(clks[ssp3], IMX_SSP3_BASE, NULL); clkdev_add_physbase(clks[fec], IMX_FEC0_BASE, NULL); clkdev_add_physbase(clks[xbus], IMX_DBGUART_BASE, NULL); clkdev_add_physbase(clks[hbus], IMX_OCOTP_BASE, NULL); clkdev_add_physbase(clks[uart], IMX_UART0_BASE, NULL); clkdev_add_physbase(clks[uart], IMX_UART1_BASE, NULL); clkdev_add_physbase(clks[uart], IMX_UART2_BASE, NULL); clkdev_add_physbase(clks[uart], IMX_UART3_BASE, NULL); clkdev_add_physbase(clks[uart], IMX_UART4_BASE, NULL); clkdev_add_physbase(clks[gpmi], MXS_GPMI_BASE, NULL); if (IS_ENABLED(CONFIG_DRIVER_VIDEO_STM)) clkdev_add_physbase(clks[lcdif_comp], IMX_FB_BASE, NULL); return 0; }