static void clk_pllv3_disable(struct clk_hw *hw) { struct clk_pllv3 *pll = to_clk_pllv3(hw); u32 val; val = readl_relaxed(pll->base); if (!pll->always_on) val &= ~BM_PLL_ENABLE; writel_relaxed(val, pll->base); if (pll->rate_req != BYPASS_RATE) clk_pllv3_power_up_down(hw, false); }
static int clk_pllv3_do_hardware(struct clk_hw *hw, bool enable) { struct clk_pllv3 *pll = to_clk_pllv3(hw); u32 val; if (enable) { if (pll->rate_req != BYPASS_RATE) clk_pllv3_power_up_down(hw, true); val = readl_relaxed(pll->base); val |= BM_PLL_ENABLE; writel_relaxed(val, pll->base); } else { val = readl_relaxed(pll->base); if (!pll->always_on) val &= ~BM_PLL_ENABLE; writel_relaxed(val, pll->base); if (pll->rate_req != BYPASS_RATE) clk_pllv3_power_up_down(hw, false); } return 0; }
static int clk_pllv3_enable(struct clk_hw *hw) { struct clk_pllv3 *pll = to_clk_pllv3(hw); u32 val; if (pll->rate_req != BYPASS_RATE) clk_pllv3_power_up_down(hw, true); val = readl_relaxed(pll->base); val |= BM_PLL_ENABLE; writel_relaxed(val, pll->base); return 0; }