static void disable_sor_periph_clocks(void)
{
clock_disable(CLK_L_HOST1X, 0, 0, 0, 0, CLK_X_DPAUX, 0);
/* Give clocks time to stabilize. */
udelay(IO_STABILIZATION_DELAY);
}
/*
* Configure PORT_1A as data with PORT_1B as the valid signal. Ensure that the
* receiver is ready using a channel end. Send a word of data, delay for a while
* and send another word to ensure the valid signals are functioning.
*/
void port_test_output(chanend c)
{
port p = port_enable(XS1_PORT_1A);
port_set_buffered(p);
port_set_transfer_width(p, 32);
port p_ready = port_enable(XS1_PORT_1B);
clock clk = clock_enable(XS1_CLKBLK_1);
clock_start(clk);
port_configure_out_strobed_master(p, p_ready, clk, 0);
chan_input_word(c); // Wait for ack
port_output(p, 0xfeedbeef);
timer tmr = timer_alloc();
timer_delay(tmr, 1000);
timer_free(tmr);
port_output(p, 0x12345678);
chan_input_word(c); // Wait for ack
port_disable(p);
port_disable(p_ready);
clock_disable(clk);
// Get information about the tile/core running the server for debug messages
unsigned tile_id = get_local_tile_id();
unsigned core_id = get_logical_core_id();
debug_printf("%x:%d: output done\n", tile_id, core_id);
}
/*
* Configure PORT_1C as data with PORT_1D as the valid signal. Test receiving
* two different words of data and check they are the correct values.
*/
void port_test_input(chanend c)
{
port p = port_enable(XS1_PORT_1C);
port_set_buffered(p);
port_set_transfer_width(p, 32);
port p_ready = port_enable(XS1_PORT_1D);
clock clk = clock_enable(XS1_CLKBLK_2);
clock_start(clk);
port_configure_in_strobed_slave(p, p_ready, clk);
chan_output_word(c, 0); // Send ack
unsigned int x = port_input(p);
if (x != 0xfeedbeef) {
debug_printf("Error %x received instead of 0xfeedbeef\n", x);
}
x = port_input(p);
if (x != 0x12345678) {
debug_printf("Error %x received instead of 0x12345678\n", x);
}
chan_output_word(c, 0); // Send ack
port_disable(p);
port_disable(p_ready);
clock_disable(clk);
// Get information about the tile/core running the server for debug messages
unsigned tile_id = get_local_tile_id();
unsigned core_id = get_logical_core_id();
debug_printf("%x:%d: input done\n", tile_id, core_id);
}
static void powerdown_handler(struct work_struct *work)
{
struct nvhost_module *mod;
mod = container_of(to_delayed_work(work),
struct nvhost_module,
powerdown);
mutex_lock(&mod->lock);
if ((atomic_read(&mod->refcount) == 0) && mod->powered) {
if (mod->desc->prepare_poweroff
&& mod->desc->prepare_poweroff(mod)) {
/* If poweroff fails, retry */
mutex_unlock(&mod->lock);
schedule_delayed_work(&mod->powerdown,
msecs_to_jiffies(
mod->desc->powerdown_delay));
return;
}
clock_disable(mod);
powergate(mod);
mod->powered = false;
if (mod->parent)
nvhost_module_idle(mod->parent);
}
mutex_unlock(&mod->lock);
}
int mmc_clock_enable_disable(unsigned id, unsigned enable)
{
if (enable) {
return clock_enable(id); //Enable mmc clock rate
} else {
return clock_disable(id); //Disable mmc clock rate
}
}
static int tegra_car_clk_disable(struct clk *clk)
{
debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
clk->id);
clock_disable(clk->id);
return 0;
}
static void powerdown_handler(struct work_struct *work)
{
struct nvhost_module *mod;
mod = container_of(to_delayed_work(work),
struct nvhost_module,
powerdown);
mutex_lock(&mod->lock);
if ((atomic_read(&mod->refcount) == 0) && mod->powered) {
if (mod->desc->prepare_poweroff)
mod->desc->prepare_poweroff(mod);
clock_disable(mod);
powergate(mod);
mod->powered = false;
if (mod->parent)
nvhost_module_idle(mod->parent);
}
mutex_unlock(&mod->lock);
}
void mdp_clock_disable(void)
{
if (!target_cont_splash_screen())
clock_disable(MDP_CLK);
clock_disable(MDP_P_CLK);
}
void clock_disable_host1x()
{
clock_disable(&_clock_host1x);
}
void clock_disable_kfuse()
{
clock_disable(&_clock_kfuse);
}
void clock_disable_sor1()
{
clock_disable(&_clock_sor1);
}
void clock_disable_sor0()
{
clock_disable(&_clock_sor0);
}
void clock_disable_sor_safe()
{
clock_disable(&_clock_sor_safe);
}
void clock_disable_tsec()
{
clock_disable(&_clock_tsec);
}
