示例#1
0
文件: mainboard.c 项目: 0ida/coreboot
static void mainboard_enable(device_t dev)
{
	dev->ops->init = &mainboard_init;

	/* set up dcache and MMU */
	/* FIXME: this should happen via resource allocator */
	exynos5250_config_l2_cache();
	mmu_init();
	mmu_config_range(0, DRAM_START, DCACHE_OFF);
	mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK);
	mmu_config_range(DMA_START >> 20, DMA_SIZE >> 20, DCACHE_OFF);
	mmu_config_range(DRAM_END, 4096 - DRAM_END, DCACHE_OFF);
	dcache_invalidate_all();
	dcache_mmu_enable();

	/* this is going to move, but we must have it now and we're
	 * not sure where */
	exception_init();

	const unsigned epll_hz = 192000000;
	const unsigned sample_rate = 48000;
	const unsigned lr_frame_size = 256;
	clock_epll_set_rate(epll_hz);
	clock_select_i2s_clk_source();
	clock_set_i2s_clk_prescaler(epll_hz, sample_rate * lr_frame_size);

	power_enable_xclkout();
}
示例#2
0
int i2s_tx_init(struct i2stx_info *pi2s_tx)
{
	int ret;
	struct exynos5_i2s *i2s_reg =
				(struct exynos5_i2s *)pi2s_tx->base_address;

	/* Initialize GPIO for I2s */
	exynos_pinmux_config(PERIPH_ID_I2S1, 0);

	/* Set EPLL Clock */
	ret = clock_epll_set_rate(pi2s_tx->audio_pll_clk);
	if (ret != 0) {
		debug("%s: epll clock set rate falied\n", __func__);
		return -1;
	}

	/* Select Clk Source for Audio1 */
	clock_select_i2s_clk_source();

	/* Set Prescaler to get MCLK */
	clock_set_i2s_clk_prescaler(pi2s_tx->audio_pll_clk,
				(pi2s_tx->samplingrate * (pi2s_tx->rfs)));

	/* Configure I2s format */
	ret = i2s_set_fmt(i2s_reg, (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
				SND_SOC_DAIFMT_CBM_CFM));
	if (ret == 0) {
		i2s_set_lr_framesize(i2s_reg, pi2s_tx->rfs);
		ret = i2s_set_samplesize(i2s_reg, pi2s_tx->bitspersample);
		if (ret != 0) {
			debug("%s:set sample rate failed\n", __func__);
			return -1;
		}

		i2s_set_bitclk_framesize(i2s_reg, pi2s_tx->bfs);
		/* disable i2s transfer flag and flush the fifo */
		i2s_txctrl(i2s_reg, I2S_TX_OFF);
		i2s_fifo(i2s_reg, FIC_TXFLUSH);
	} else
		debug("%s: failed\n", __func__);

	return ret;
}
示例#3
0
static void mainboard_enable(device_t dev)
{
	dev->ops->init = &mainboard_init;

	/* set up dcache and MMU */
	/* FIXME: this should happen via resource allocator */
	exynos5250_config_l2_cache();
	mmu_init();
	mmu_config_range(0, DRAM_START, DCACHE_OFF);
	mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK);
	mmu_config_range((uintptr_t)_dma_coherent/MiB,
			 _dma_coherent_size/MiB, DCACHE_OFF);
	mmu_config_range(DRAM_END, 4096 - DRAM_END, DCACHE_OFF);
	dcache_mmu_enable();

	const unsigned epll_hz = 192000000;
	const unsigned sample_rate = 48000;
	const unsigned lr_frame_size = 256;
	clock_epll_set_rate(epll_hz);
	clock_select_i2s_clk_source();
	clock_set_i2s_clk_prescaler(epll_hz, sample_rate * lr_frame_size);

	power_enable_xclkout();
}
示例#4
0
void main(void)
{
	console_init();
	printk(BIOS_INFO, "hello from ramstage; now with deluxe exception handling.\n");

	/* this is going to move, but we must have it now and we're not sure where */
	exception_init();
	/* place at top of physical memory */
	high_tables_size = CONFIG_COREBOOT_TABLES_SIZE;
	high_tables_base = CONFIG_SYS_SDRAM_BASE +
			((CONFIG_DRAM_SIZE_MB << 20UL) * CONFIG_NR_DRAM_BANKS) -
			CONFIG_COREBOOT_TABLES_SIZE;

	const unsigned epll_hz = 192000000;
	const unsigned sample_rate = 48000;
	const unsigned lr_frame_size = 256;
	clock_epll_set_rate(epll_hz);
	clock_select_i2s_clk_source();
	clock_set_i2s_clk_prescaler(epll_hz, sample_rate * lr_frame_size);

	power_enable_xclkout();

	hardwaremain(0);
}
示例#5
0
/* this happens after cpu_init where exynos resources are set */
static void mainboard_init(device_t dev)
{
	int dp_tries;
	struct s5p_dp_device dp_device = {
		.base = (struct exynos5_dp *)EXYNOS5250_DP1_BASE,
		.video_info = &dp_video_info,
	};
	void *fb_addr = (void *)(get_fb_base_kb() * KiB);

	gpio_init();

	i2c_init(TPS65090_BUS, I2C_0_SPEED, I2C_SLAVE);
	i2c_init(7, I2C_0_SPEED, I2C_SLAVE);

	tmu_init(&exynos5250_tmu_info);

	/* Clock Gating all the unused IP's to save power */
	clock_gate();

	/* Disable USB3.0 PLL to save 250mW of power */
	disable_usb30_pll();

	set_vbe_mode_info_valid(&edid, (uintptr_t)fb_addr);

	lcd_vdd();

	// FIXME: should timeout
	do {
		udelay(50);
	} while (!exynos_dp_hotplug());

	exynos_dp_bridge_setup();
	for (dp_tries = 1; dp_tries <= MAX_DP_TRIES; dp_tries++) {
		exynos_dp_bridge_init();
		if (exynos_dp_hotplug()) {
			exynos_dp_reset();
			continue;
		}

		if (dp_controller_init(&dp_device))
			continue;

		udelay(LCD_T3_DELAY_MS * 1000);

		backlight_vdd();
		backlight_pwm();
		backlight_en();
		/* if we're here, we're successful */
		break;
	}

	if (dp_tries > MAX_DP_TRIES)
		printk(BIOS_ERR, "%s: Failed to set up displayport\n", __func__);

	// Uncomment to get excessive GPIO output:
	// gpio_info();
}

static void mainboard_enable(device_t dev)
{
	dev->ops->init = &mainboard_init;

	/* set up dcache and MMU */
	/* FIXME: this should happen via resource allocator */
	exynos5250_config_l2_cache();
	mmu_init();
	mmu_config_range(0, DRAM_START, DCACHE_OFF);
	mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK);
	mmu_config_range(DRAM_END, 4096 - DRAM_END, DCACHE_OFF);
	dcache_invalidate_all();
	dcache_mmu_enable();

	/* this is going to move, but we must have it now and we're
	 * not sure where */
	exception_init();

	const unsigned epll_hz = 192000000;
	const unsigned sample_rate = 48000;
	const unsigned lr_frame_size = 256;
	clock_epll_set_rate(epll_hz);
	clock_select_i2s_clk_source();
	clock_set_i2s_clk_prescaler(epll_hz, sample_rate * lr_frame_size);

	power_enable_xclkout();
}