void clock_init(void)
{
#ifdef STM32_HSE_CLOCK
clock_set_osc(OSC_PLL, OSC_HSE);
#else
clock_set_osc(OSC_HSI, OSC_INIT);
#endif
}
static int command_clock(int argc, char **argv)
{
if (argc >= 2) {
if (!strcasecmp(argv[1], "hsi"))
clock_set_osc(OSC_HSI);
else if (!strcasecmp(argv[1], "msi"))
clock_set_osc(OSC_MSI);
else
return EC_ERROR_PARAM1;
}
ccprintf("Clock frequency is now %d Hz\n", freq);
return EC_SUCCESS;
}
void clock_init(void)
{
/*
* The initial state :
* SYSCLK from MSI (=2MHz), no divider on AHB, APB1, APB2
* PLL unlocked, RTC enabled on LSE
*/
/* Switch to high-speed oscillator */
clock_set_osc(1);
}
static int command_clock(int argc, char **argv)
{
if (argc >= 2) {
if (!strcasecmp(argv[1], "hsi"))
clock_set_osc(OSC_HSI, OSC_INIT);
else if (!strcasecmp(argv[1], "msi"))
clock_set_osc(OSC_MSI, OSC_INIT);
#ifdef STM32_HSE_CLOCK
else if (!strcasecmp(argv[1], "hse"))
clock_set_osc(OSC_HSE, OSC_INIT);
else if (!strcasecmp(argv[1], "pll"))
clock_set_osc(OSC_PLL, OSC_HSE);
#endif
else
return EC_ERROR_PARAM1;
}
ccprintf("Clock frequency is now %d Hz\n", freq);
return EC_SUCCESS;
}
void clock_enable_module(enum module_id module, int enable)
{
static uint32_t clock_mask;
int new_mask;
if (enable)
new_mask = clock_mask | (1 << module);
else
new_mask = clock_mask & ~(1 << module);
/* Only change clock if needed */
if ((!!new_mask) != (!!clock_mask)) {
/* Flush UART before switching clock speed */
cflush();
clock_set_osc(new_mask ? OSC_HSI : OSC_MSI);
}
clock_mask = new_mask;
}
