/* * EthernetDeviceのファクトリー関数。インターフェイスを生成できればtrue * */ NyLPC_TBool EthDev_LPC4088_getInterface( const struct TiEthernetDevice** o_dev) { int regv, tout; unsigned int clock = clockselect(); LPC_SC->PCONP |= 0x40000000; /* Power Up the EMAC controller. */ LPC_IOCON->P1_0 &= ~0x07; /* ENET I/O config */ LPC_IOCON->P1_0 |= 0x01; /* ENET_TXD0 */ LPC_IOCON->P1_1 &= ~0x07; LPC_IOCON->P1_1 |= 0x01; /* ENET_TXD1 */ LPC_IOCON->P1_4 &= ~0x07; LPC_IOCON->P1_4 |= 0x01; /* ENET_TXEN */ LPC_IOCON->P1_8 &= ~0x07; LPC_IOCON->P1_8 |= 0x01; /* ENET_CRS */ LPC_IOCON->P1_9 &= ~0x07; LPC_IOCON->P1_9 |= 0x01; /* ENET_RXD0 */ LPC_IOCON->P1_10 &= ~0x07; LPC_IOCON->P1_10 |= 0x01; /* ENET_RXD1 */ LPC_IOCON->P1_14 &= ~0x07; LPC_IOCON->P1_14 |= 0x01; /* ENET_RX_ER */ LPC_IOCON->P1_15 &= ~0x07; LPC_IOCON->P1_15 |= 0x01; /* ENET_REF_CLK */ LPC_IOCON->P1_16 &= ~0x07; /* ENET/PHY I/O config */ LPC_IOCON->P1_16 |= 0x01; /* ENET_MDC */ LPC_IOCON->P1_17 &= ~0x07; LPC_IOCON->P1_17 |= 0x01; /* ENET_MDIO */ /* Reset all EMAC internal modules. */ LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES; LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES | CR_PASS_RUNT_FRM; for (tout = 100; tout; tout--) { __NOP(); } /* A short delay */ /* Initialize MAC control registers. */ LPC_EMAC->MAC1 = MAC1_PASS_ALL; LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN; LPC_EMAC->MAXF = ETH_MAX_FLEN; LPC_EMAC->CLRT = CLRT_DEF; LPC_EMAC->IPGR = IPGR_DEF; /* Enable Reduced MII interface. */ LPC_EMAC->MCFG = (clock << 0x2) & MCFG_CLK_SEL; /* Set clock */ LPC_EMAC->MCFG |= MCFG_RES_MII; /* and reset */ LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM |CR_PASS_RX_FILT; /* Enable Reduced MII interface. */ for (tout = 100; tout; tout--) { __NOP(); } /* A short delay */ LPC_EMAC->MCFG = (clock << 0x2) & MCFG_CLK_SEL; LPC_EMAC->MCMD = 0; LPC_EMAC->SUPP = SUPP_RES_RMII; /* Reset Reduced MII Logic. */ for (tout = 100; tout; tout--) { __NOP(); } /* A short delay */ LPC_EMAC->SUPP = SUPP_SPEED; phy_write(PHY_REG_BMCR, PHY_BMCR_RESET); /* perform PHY reset */ for(tout = 0x20000; ; tout--) { /* Wait for hardware reset to end. */ regv = phy_read(PHY_REG_BMCR); if(regv < 0 || tout == 0) { return NyLPC_TBool_FALSE; /* Error */ } if(!(regv & PHY_BMCR_RESET)) { break; /* Reset complete. */ } } phy_id = (phy_read(PHY_REG_IDR1) << 16); phy_id |= (phy_read(PHY_REG_IDR2) & 0XFFF0); switch(phy_id){ case DP83848C_ID: *o_dev=&_interface_DP83848C; break; case LAN8720_ID: *o_dev=&_interface_LAN8720; break; default: return NyLPC_TBool_FALSE; /* Error */ } LPC_EMAC->TxProduceIndex = 0; LPC_EMAC->RxConsumeIndex = 0; return NyLPC_TBool_TRUE; }
/*---------------------------------------------------------------------------- Ethernet Device initialize *----------------------------------------------------------------------------*/ int ethernet_init() { int regv, tout; char mac[ETHERNET_ADDR_SIZE]; unsigned int clock = clockselect(); LPC_SC->PCONP |= 0x40000000; /* Power Up the EMAC controller. */ LPC_PINCON->PINSEL2 = 0x50150105; /* Enable P1 Ethernet Pins. */ LPC_PINCON->PINSEL3 = (LPC_PINCON->PINSEL3 & ~0x0000000F) | 0x00000005; /* Reset all EMAC internal modules. */ LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES; LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES | CR_PASS_RUNT_FRM; for(tout = 100; tout; tout--) __NOP(); /* A short delay after reset. */ LPC_EMAC->MAC1 = MAC1_PASS_ALL; /* Initialize MAC control registers. */ LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN; LPC_EMAC->MAXF = ETH_MAX_FLEN; LPC_EMAC->CLRT = CLRT_DEF; LPC_EMAC->IPGR = IPGR_DEF; LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM; /* Enable Reduced MII interface. */ LPC_EMAC->MCFG = (clock << 0x2) & MCFG_CLK_SEL; /* Set clock */ LPC_EMAC->MCFG |= MCFG_RES_MII; /* and reset */ for(tout = 100; tout; tout--) __NOP(); /* A short delay */ LPC_EMAC->MCFG = (clock << 0x2) & MCFG_CLK_SEL; LPC_EMAC->MCMD = 0; LPC_EMAC->SUPP = SUPP_RES_RMII; /* Reset Reduced MII Logic. */ for (tout = 100; tout; tout--) __NOP(); /* A short delay */ LPC_EMAC->SUPP = 0; phy_write(PHY_REG_BMCR, PHY_BMCR_RESET); /* perform PHY reset */ for(tout = 0x20000; ; tout--) { /* Wait for hardware reset to end. */ regv = phy_read(PHY_REG_BMCR); if(regv < 0 || tout == 0) { return -1; /* Error */ } if(!(regv & PHY_BMCR_RESET)) { break; /* Reset complete. */ } } phy_id = (phy_read(PHY_REG_IDR1) << 16); phy_id |= (phy_read(PHY_REG_IDR2) & 0XFFF0); if (phy_id != DP83848C_ID && phy_id != LAN8720_ID) { error("Unknown Ethernet PHY (%x)", (unsigned int)phy_id); } ethernet_set_link(-1, 0); /* Set the Ethernet MAC Address registers */ ethernet_address(mac); LPC_EMAC->SA0 = ((uint32_t)mac[5] << 8) | (uint32_t)mac[4]; LPC_EMAC->SA1 = ((uint32_t)mac[3] << 8) | (uint32_t)mac[2]; LPC_EMAC->SA2 = ((uint32_t)mac[1] << 8) | (uint32_t)mac[0]; txdscr_init(); /* initialize DMA TX Descriptor */ rxdscr_init(); /* initialize DMA RX Descriptor */ LPC_EMAC->RxFilterCtrl = RFC_UCAST_EN | RFC_MCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN; /* Receive Broadcast, Perfect Match Packets */ LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE; /* Enable EMAC interrupts. */ LPC_EMAC->IntClear = 0xFFFF; /* Reset all interrupts */ LPC_EMAC->Command |= (CR_RX_EN | CR_TX_EN); /* Enable receive and transmit mode of MAC Ethernet core */ LPC_EMAC->MAC1 |= MAC1_REC_EN; #if NEW_LOGIC rx_consume_offset = -1; tx_produce_offset = -1; #else send_doff = 0; send_idx = -1; send_size = 0; receive_soff = 0; receive_idx = -1; #endif return 0; }