/*
* hardware specific access to control-lines
*/
static void ep7312_hwcontrol(struct mtd_info *mtd, int cmd)
{
switch(cmd) {
case NAND_CTL_SETCLE:
clps_writeb(clps_readb(ep7312_pxdr) | 0x10, ep7312_pxdr);
break;
case NAND_CTL_CLRCLE:
clps_writeb(clps_readb(ep7312_pxdr) & ~0x10, ep7312_pxdr);
break;
case NAND_CTL_SETALE:
clps_writeb(clps_readb(ep7312_pxdr) | 0x20, ep7312_pxdr);
break;
case NAND_CTL_CLRALE:
clps_writeb(clps_readb(ep7312_pxdr) & ~0x20, ep7312_pxdr);
break;
case NAND_CTL_SETNCE:
clps_writeb((clps_readb(ep7312_pxdr) | 0x80) & ~0x40, ep7312_pxdr);
break;
case NAND_CTL_CLRNCE:
clps_writeb((clps_readb(ep7312_pxdr) | 0x80) | 0x40, ep7312_pxdr);
break;
}
}
/*
* hardware specific access to control-lines
*
* NAND_NCE: bit 0 -> bit 6 (bit 7 = 1)
* NAND_CLE: bit 1 -> bit 4
* NAND_ALE: bit 2 -> bit 5
*/
static void ep7312_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
struct nand_chip *chip = mtd->priv;
if (ctrl & NAND_CTRL_CHANGE) {
unsigned char bits = 0x80;
bits |= (ctrl & (NAND_CLE | NAND_ALE)) << 3;
bits |= (ctrl & NAND_NCE) ? 0x00 : 0x40;
clps_writeb((clps_readb(ep7312_pxdr) & 0xF0) | bits,
ep7312_pxdr);
}
if (cmd != NAND_CMD_NONE)
writeb(cmd, chip->IO_ADDR_W);
}
int setup_cs43l42(void)
{
volatile long u;
volatile char port_d;
printk("cs43l42: init dac\n");
port_d = clps_readb(PDDR) & ~(SCL | SDA);
/* enable codec_en# */
reset_cs43l42();
/* make SDA & SCL outputs */
make_scl_sda_outputs();
/*
* enable the two wire serial interface on the CS43L42
* by setting the CP_EN bit (bit 0) of register 1
*/
cs43l42_i2c_write(ADDR_CS43L42, CS43L42_PWRCTL, 0xd2);
/* set the data format to left justified */
cs43l42_i2c_write(ADDR_CS43L42, 0x0b, 0x02);
/* power on the DAC */
cs43l42_i2c_write(ADDR_CS43L42, CS43L42_PWRCTL, 0xd0);
/* delay while the DAC initializes */
for(u = 0; u < 15; u++)
udelay(5);
cs43l42_i2c_write(ADDR_CS43L42, 2, 0xf1);
cs43l42_i2c_write(ADDR_CS43L42, 3, 0xf1);
#if 0
cs43l42_dump_regs();
printk("syscon1 %08x\n", clps_readl(SYSCON1));
printk("syscon2 %08x\n", clps_readl(SYSCON2));
printk("syscon3 %08x\n", clps_readl(SYSCON3));
#endif
/* restore original port D value */
port_d |= clps_readb(PDDR);
clps_writeb(port_d, PDDR);
printk("cs43l42: init dac complete\n");
return 0;
}
static void p720t_leds_event(led_event_t ledevt)
{
unsigned long flags;
u32 pddr;
local_irq_save(flags);
switch(ledevt) {
case led_idle_start:
break;
case led_idle_end:
break;
case led_timer:
pddr = clps_readb(PDDR);
clps_writeb(pddr ^ 1, PDDR);
break;
default:
break;
}
local_irq_restore(flags);
}
/*
* Main initialization routine
*/
static int __init ep7312_init(void)
{
struct nand_chip *this;
const char *part_type = 0;
int mtd_parts_nb = 0;
struct mtd_partition *mtd_parts = 0;
void __iomem *ep7312_fio_base;
/* Allocate memory for MTD device structure and private data */
ep7312_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
if (!ep7312_mtd) {
;
return -ENOMEM;
}
/* map physical address */
ep7312_fio_base = ioremap(ep7312_fio_pbase, SZ_1K);
if (!ep7312_fio_base) {
;
kfree(ep7312_mtd);
return -EIO;
}
/* Get pointer to private data */
this = (struct nand_chip *)(&ep7312_mtd[1]);
/* Initialize structures */
memset(ep7312_mtd, 0, sizeof(struct mtd_info));
memset(this, 0, sizeof(struct nand_chip));
/* Link the private data with the MTD structure */
ep7312_mtd->priv = this;
ep7312_mtd->owner = THIS_MODULE;
/*
* Set GPIO Port B control register so that the pins are configured
* to be outputs for controlling the NAND flash.
*/
clps_writeb(0xf0, ep7312_pxddr);
/* insert callbacks */
this->IO_ADDR_R = ep7312_fio_base;
this->IO_ADDR_W = ep7312_fio_base;
this->cmd_ctrl = ep7312_hwcontrol;
this->dev_ready = ep7312_device_ready;
/* 15 us command delay time */
this->chip_delay = 15;
/* Scan to find existence of the device */
if (nand_scan(ep7312_mtd, 1)) {
iounmap((void *)ep7312_fio_base);
kfree(ep7312_mtd);
return -ENXIO;
}
ep7312_mtd->name = "edb7312-nand";
mtd_parts_nb = parse_mtd_partitions(ep7312_mtd, part_probes, &mtd_parts, 0);
if (mtd_parts_nb > 0)
part_type = "command line";
else
mtd_parts_nb = 0;
if (mtd_parts_nb == 0) {
mtd_parts = partition_info;
mtd_parts_nb = NUM_PARTITIONS;
part_type = "static";
}
/* Register the partitions */
;
mtd_device_register(ep7312_mtd, mtd_parts, mtd_parts_nb);
/* Return happy */
return 0;
}
/*
* Main initialization routine
*/
static int __init ep7312_init (void)
{
struct nand_chip *this;
const char *part_type = 0;
int mtd_parts_nb = 0;
struct mtd_partition *mtd_parts = 0;
int ep7312_fio_base;
/* Allocate memory for MTD device structure and private data */
ep7312_mtd = kmalloc(sizeof(struct mtd_info) +
sizeof(struct nand_chip),
GFP_KERNEL);
if (!ep7312_mtd) {
printk("Unable to allocate EDB7312 NAND MTD device structure.\n");
return -ENOMEM;
}
/* map physical adress */
ep7312_fio_base = (unsigned long)ioremap(ep7312_fio_pbase, SZ_1K);
if(!ep7312_fio_base) {
printk("ioremap EDB7312 NAND flash failed\n");
kfree(ep7312_mtd);
return -EIO;
}
/* Get pointer to private data */
this = (struct nand_chip *) (&ep7312_mtd[1]);
/* Initialize structures */
memset((char *) ep7312_mtd, 0, sizeof(struct mtd_info));
memset((char *) this, 0, sizeof(struct nand_chip));
/* Link the private data with the MTD structure */
ep7312_mtd->priv = this;
/*
* Set GPIO Port B control register so that the pins are configured
* to be outputs for controlling the NAND flash.
*/
clps_writeb(0xf0, ep7312_pxddr);
/* insert callbacks */
this->IO_ADDR_R = ep7312_fio_base;
this->IO_ADDR_W = ep7312_fio_base;
this->hwcontrol = ep7312_hwcontrol;
this->dev_ready = ep7312_device_ready;
/* 15 us command delay time */
this->chip_delay = 15;
/* Scan to find existence of the device */
if (nand_scan (ep7312_mtd, 1)) {
iounmap((void *)ep7312_fio_base);
kfree (ep7312_mtd);
return -ENXIO;
}
/* Allocate memory for internal data buffer */
this->data_buf = kmalloc (sizeof(u_char) * (ep7312_mtd->oobblock + ep7312_mtd->oobsize), GFP_KERNEL);
if (!this->data_buf) {
printk("Unable to allocate NAND data buffer for EDB7312.\n");
iounmap((void *)ep7312_fio_base);
kfree (ep7312_mtd);
return -ENOMEM;
}
#ifdef CONFIG_PARTITIONS
ep7312_mtd->name = "edb7312-nand";
mtd_parts_nb = parse_mtd_partitions(ep7312_mtd, part_probes,
&mtd_parts, 0);
if (mtd_parts_nb > 0)
part_type = "command line";
else
mtd_parts_nb = 0;
#endif
if (mtd_parts_nb == 0) {
mtd_parts = partition_info;
mtd_parts_nb = NUM_PARTITIONS;
part_type = "static";
}
/* Register the partitions */
printk(KERN_NOTICE "Using %s partition definition\n", part_type);
add_mtd_partitions(ep7312_mtd, mtd_parts, mtd_parts_nb);
/* Return happy */
return 0;
}
void kgdb_serial_putchar(unsigned char ch)
{
while (clps_readl(KGDB_SYSFLG) & 0x00800000);
clps_writeb(ch, KGDB_UART);
}
