static void t102xqds_set_monitor_port(enum fsl_diu_monitor_port port) { struct device_node *pixis_node; void __iomem *pixis; pixis_node = of_find_compatible_node(NULL, NULL, "fsl,tetra-fpga"); if (!pixis_node) { pr_err("t102xqds: missing pixis node\n"); goto exit; } pixis = of_iomap(pixis_node, 0); of_node_put(pixis_node); if (!pixis) { pr_err("t102xqds: could not map pixis registers\n"); goto exit; } /* Route I2C4 to DIU system as HSYNC/VSYNC */ clrbits8(pixis + BRDCFG5, BRDCFG5_IMX_DIU_LOW); setbits8(pixis + BRDCFG5, BRDCFG5_IMX_DIU_HIGH); switch (port) { case FSL_DIU_PORT_DVI: /* Enable the DVI(HDMI) port, disable the DFP and * the backlight */ clrbits8(pixis + BRDCFG15, BRDCFG15_LCD_ENABLED); setbits8(pixis + BRDCFG15, BRDCFG15_LCD_PD); clrbits8(pixis + BRDCFG15, BRDCFG15_DIUSEL_HDMI); break; case FSL_DIU_PORT_LVDS: /* * LVDS also needs backlight enabled, otherwise the display * will be blank. */ /* Enable the DFP port, disable the DVI*/ setbits8(pixis + BRDCFG15, BRDCFG15_DIUSEL_LVDS); clrbits8(pixis + BRDCFG15, BRDCFG15_LCD_PD); setbits8(pixis + BRDCFG15, BRDCFG15_LCD_ENABLED); break; default: pr_err("%s: Unsupported monitor port %i\n", __func__, port); } iounmap(pixis); exit: return; }
static void direct_access_pixis_reset_pcie_slot(void) { struct device_node *pixis_node; void __iomem *pixis; /* Map the pixis registers. */ pixis_node = of_find_compatible_node(NULL, NULL, "fsl,p1022ds-fpga"); if (!pixis_node) { pr_err("p1022ds: missing pixis node\n"); return; } pixis = of_iomap(pixis_node, 0); of_node_put(pixis_node); if (!pixis) { pr_err("p1022ds: could not map pixis registers\n"); return; } /* Rset PCIE slot */ /* power down pcie slot */ clrbits8(pixis + PX_RST, PX_RST_PCIE); /* power up pcie slot */ setbits8(pixis + PX_RST, PX_RST_PCIE); iounmap(pixis); }
static int cpm_uart_startup(struct uart_port *port) { int retval; struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; pr_debug("CPM uart[%d]:startup\n", port->line); /* If the port is not the console, make sure rx is disabled. */ if (!(pinfo->flags & FLAG_CONSOLE)) { /* Disable UART rx */ if (IS_SMC(pinfo)) { clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN); clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX); } else { clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR); clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_RX); } cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX); } /* Install interrupt handler. */ retval = request_irq(port->irq, cpm_uart_int, 0, "cpm_uart", port); if (retval) return retval; /* Startup rx-int */ if (IS_SMC(pinfo)) { setbits8(&pinfo->smcp->smc_smcm, SMCM_RX); setbits16(&pinfo->smcp->smc_smcmr, (SMCMR_REN | SMCMR_TEN)); } else { setbits16(&pinfo->sccp->scc_sccm, UART_SCCM_RX); setbits32(&pinfo->sccp->scc_gsmrl, (SCC_GSMRL_ENR | SCC_GSMRL_ENT)); } return 0; }
/* * Initialize port. This is called from early_console stuff * so we have to be careful here ! */ static int cpm_uart_request_port(struct uart_port *port) { struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; int ret; pr_debug("CPM uart[%d]:request port\n", port->line); if (pinfo->flags & FLAG_CONSOLE) return 0; if (IS_SMC(pinfo)) { clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX | SMCM_TX); clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN); } else { clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX); clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT); } ret = cpm_uart_allocbuf(pinfo, 0); if (ret) return ret; cpm_uart_initbd(pinfo); if (IS_SMC(pinfo)) cpm_uart_init_smc(pinfo); else cpm_uart_init_scc(pinfo); return 0; }
static int __init ppc460ex_canyonlands_fixup(void) { u8 __iomem *bcsr ; void __iomem *vaddr; struct device_node *np; int ret = 0; np = of_find_compatible_node(NULL, NULL, "amcc,ppc460ex-bcsr"); if (!np) { printk(KERN_ERR "failed did not find amcc, ppc460ex bcsr node\n"); return -ENODEV; } bcsr = of_iomap(np, 0); of_node_put(np); if (!bcsr) { printk(KERN_CRIT "Could not remap bcsr\n"); ret = -ENODEV; goto err_bcsr; } np = of_find_compatible_node(NULL, NULL, "ibm,ppc4xx-gpio"); if (!np) { printk(KERN_ERR "failed did not find ibm,ppc4xx-gpio node\n"); return -ENODEV; } vaddr = of_iomap(np, 0); of_node_put(np); if (!vaddr) { printk(KERN_CRIT "Could not get gpio node address\n"); ret = -ENODEV; goto err_gpio; } /* Disable USB, through the BCSR7 bits */ setbits8(&bcsr[7], BCSR_USB_EN); /* Wait for a while after reset */ msleep(100); /* Enable USB here */ clrbits8(&bcsr[7], BCSR_USB_EN); /* * Configure multiplexed gpio16 and gpio19 as alternate1 output * source after USB reset. In this configuration gpio16 will be * USB2HStop and gpio19 will be USB2DStop. For more details refer to * table 34-7 of PPC460EX user manual. */ setbits32((vaddr + GPIO0_OSRH), 0x42000000); setbits32((vaddr + GPIO0_TSRH), 0x42000000); err_gpio: iounmap(vaddr); err_bcsr: iounmap(bcsr); return ret; }
void sbc8560_rstcr_restart(char * cmd) { local_irq_disable(); if(brstcr) clrbits8(brstcr, 0x80); while(1); }
static void fhci_stop_sof_timer(struct fhci_hcd *fhci) { fhci_dbg(fhci, "-> %s\n", __func__); clrbits8(&fhci->regs->usb_mod, USB_MODE_SFTE); qe_stop_timer(fhci->timer); fhci_dbg(fhci, "<- %s\n", __func__); }
static void ep8248e_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output) { if (output) clrbits8(&ep8248e_bcsr[8], BCSR8_MDIO_READ); else setbits8(&ep8248e_bcsr[8], BCSR8_MDIO_READ); /* Read back to flush the write. */ in_8(&ep8248e_bcsr[8]); }
static void ep8248e_set_mdc(struct mdiobb_ctrl *ctrl, int level) { if (level) setbits8(&ep8248e_bcsr[8], BCSR8_MDIO_CLOCK); else clrbits8(&ep8248e_bcsr[8], BCSR8_MDIO_CLOCK); /* Read back to flush the write. */ in_8(&ep8248e_bcsr[8]); }
static void ep8248e_set_mdio_data(struct mdiobb_ctrl *ctrl, int data) { if (data) setbits8(&ep8248e_bcsr[8], BCSR8_MDIO_DATA); else clrbits8(&ep8248e_bcsr[8], BCSR8_MDIO_DATA); /* Read back to flush the write. */ in_8(&ep8248e_bcsr[8]); }
/* * Stop receiver */ static void cpm_uart_stop_rx(struct uart_port *port) { struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; smc_t __iomem *smcp = pinfo->smcp; scc_t __iomem *sccp = pinfo->sccp; pr_debug("CPM uart[%d]:stop rx\n", port->line); if (IS_SMC(pinfo)) clrbits8(&smcp->smc_smcm, SMCM_RX); else clrbits16(&sccp->scc_sccm, UART_SCCM_RX); }
static void indirect_access_pixis_reset_pcie_slot(void) { if (!verify_pixis_indirect_access_address()) { WARN_ON(1); return; } /* Set FPGA access address */ out_8(lbc_lcs0_ba, PX_RST); /* power down pcie slot */ clrbits8(lbc_lcs1_ba, PX_RST_PCIE); /* power up pcie slot */ setbits8(lbc_lcs1_ba, PX_RST_PCIE); }
static void __init mpc85xx_rds_setup_arch(void) { struct device_node *np; if (ppc_md.progress) ppc_md.progress("p1023_rds_setup_arch()", 0); /* */ np = of_find_node_by_name(NULL, "bcsr"); if (np != NULL) { static u8 __iomem *bcsr_regs; bcsr_regs = of_iomap(np, 0); of_node_put(np); if (!bcsr_regs) { printk(KERN_ERR "BCSR: Failed to map bcsr register space\n"); return; } else { #define BCSR15_I2C_BUS0_SEG_CLR 0x07 #define BCSR15_I2C_BUS0_SEG2 0x02 /* */ #ifdef CONFIG_RTC_CLASS /* */ clrbits8(&bcsr_regs[15], BCSR15_I2C_BUS0_SEG_CLR); setbits8(&bcsr_regs[15], BCSR15_I2C_BUS0_SEG2); #endif iounmap(bcsr_regs); } } #ifdef CONFIG_PCI for_each_compatible_node(np, "pci", "fsl,p1023-pcie") fsl_add_bridge(np, 0); #endif mpc85xx_smp_init(); }
/* ************************************************************************ * * Setup the architecture * */ static void __init mpc85xx_rds_setup_arch(void) { struct device_node *np; if (ppc_md.progress) ppc_md.progress("p1023_rds_setup_arch()", 0); /* Map BCSR area */ np = of_find_node_by_name(NULL, "bcsr"); if (np != NULL) { static u8 __iomem *bcsr_regs; bcsr_regs = of_iomap(np, 0); of_node_put(np); if (!bcsr_regs) { printk(KERN_ERR "BCSR: Failed to map bcsr register space\n"); return; } else { #define BCSR15_I2C_BUS0_SEG_CLR 0x07 #define BCSR15_I2C_BUS0_SEG2 0x02 /* * Note: Accessing exclusively i2c devices. * * The i2c controller selects initially ID EEPROM in the u-boot; * but if menu configuration selects RTC support in the kernel, * the i2c controller switches to select RTC chip in the kernel. */ #ifdef CONFIG_RTC_CLASS /* Enable RTC chip on the segment #2 of i2c */ clrbits8(&bcsr_regs[15], BCSR15_I2C_BUS0_SEG_CLR); setbits8(&bcsr_regs[15], BCSR15_I2C_BUS0_SEG2); #endif iounmap(bcsr_regs); } } #ifdef CONFIG_PCI for_each_compatible_node(np, "pci", "fsl,p1023-pcie") fsl_add_bridge(np, 0); #endif mpc85xx_smp_init(); }
/* ************************************************************************ * * Setup the architecture * */ static void __init mpc832x_sys_setup_arch(void) { struct device_node *np; u8 __iomem *bcsr_regs = NULL; if (ppc_md.progress) ppc_md.progress("mpc832x_sys_setup_arch()", 0); /* Map BCSR area */ np = of_find_node_by_name(NULL, "bcsr"); if (np) { struct resource res; of_address_to_resource(np, 0, &res); bcsr_regs = ioremap(res.start, res.end - res.start +1); of_node_put(np); } #ifdef CONFIG_PCI for_each_compatible_node(np, "pci", "fsl,mpc8349-pci") mpc83xx_add_bridge(np); #endif #ifdef CONFIG_QUICC_ENGINE qe_reset(); if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) { par_io_init(np); of_node_put(np); for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;) par_io_of_config(np); } if ((np = of_find_compatible_node(NULL, "network", "ucc_geth")) != NULL) { /* Reset the Ethernet PHYs */ #define BCSR8_FETH_RST 0x50 clrbits8(&bcsr_regs[8], BCSR8_FETH_RST); udelay(1000); setbits8(&bcsr_regs[8], BCSR8_FETH_RST); iounmap(bcsr_regs); of_node_put(np); } #endif /* CONFIG_QUICC_ENGINE */ }
static int mpc837xmds_usb_cfg(void) { struct device_node *np; const void *phy_type, *mode; void __iomem *bcsr_regs = NULL; u8 bcsr12; int ret; ret = mpc837x_usb_cfg(); if (ret) return ret; /* Map BCSR area */ np = of_find_compatible_node(NULL, NULL, "fsl,mpc837xmds-bcsr"); if (np) { bcsr_regs = of_iomap(np, 0); of_node_put(np); } if (!bcsr_regs) return -1; np = of_find_node_by_name(NULL, "usb"); if (!np) { ret = -ENODEV; goto out; } phy_type = of_get_property(np, "phy_type", NULL); if (phy_type && !strcmp(phy_type, "ulpi")) { clrbits8(bcsr_regs + 12, BCSR12_USB_SER_PIN); } else if (phy_type && !strcmp(phy_type, "serial")) { mode = of_get_property(np, "dr_mode", NULL); bcsr12 = in_8(bcsr_regs + 12) & ~BCSR12_USB_SER_MASK; bcsr12 |= BCSR12_USB_SER_PIN; if (mode && !strcmp(mode, "peripheral")) bcsr12 |= BCSR12_USB_SER_DEVICE; out_8(bcsr_regs + 12, bcsr12); } else { printk(KERN_ERR "USB DR: unsupported PHY\n"); } of_node_put(np); out: iounmap(bcsr_regs); return ret; }
/* * Shutdown the uart */ static void cpm_uart_shutdown(struct uart_port *port) { struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; pr_debug("CPM uart[%d]:shutdown\n", port->line); /* free interrupt handler */ free_irq(port->irq, port); /* If the port is not the console, disable Rx and Tx. */ if (!(pinfo->flags & FLAG_CONSOLE)) { /* Wait for all the BDs marked sent */ while(!cpm_uart_tx_empty(port)) { set_current_state(TASK_UNINTERRUPTIBLE); schedule_timeout(2); } if (pinfo->wait_closing) cpm_uart_wait_until_send(pinfo); /* Stop uarts */ if (IS_SMC(pinfo)) { smc_t __iomem *smcp = pinfo->smcp; clrbits16(&smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN); clrbits8(&smcp->smc_smcm, SMCM_RX | SMCM_TX); } else { scc_t __iomem *sccp = pinfo->sccp; clrbits32(&sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT); clrbits16(&sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX); } /* Shut them really down and reinit buffer descriptors */ if (IS_SMC(pinfo)) { out_be16(&pinfo->smcup->smc_brkcr, 0); cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX); } else { out_be16(&pinfo->sccup->scc_brkcr, 0); cpm_line_cr_cmd(pinfo, CPM_CR_GRA_STOP_TX); } cpm_uart_initbd(pinfo); } }
/** * t1042rdb_set_monitor_port: switch the output to a different monitor port */ static void t1042rdb_set_monitor_port(enum fsl_diu_monitor_port port) { struct device_node *cpld_node; static void __iomem *cpld_base; cpld_node = of_find_matching_node_and_match(NULL, corenet_cpld_matches, NULL); if (!cpld_node) { pr_err("%s: Missing CPLD node\n", __func__); return; } cpld_base = of_iomap(cpld_node, 0); if (!cpld_base) { pr_err("%s: Could not map cpld registers\n", __func__); goto exit; } switch (port) { case FSL_DIU_PORT_DVI: /* Enable the DVI(HDMI) port, disable the DFP and * the backlight */ clrbits8(cpld_base + CPLD_DIUCSR, CPLD_DIUCSR_DVIEN); break; case FSL_DIU_PORT_LVDS: /* * LVDS also needs backlight enabled, otherwise the display * will be blank. */ /* Enable the DFP port, disable the DVI*/ setbits8(cpld_base + CPLD_DIUCSR, 0x01 << 8); setbits8(cpld_base + CPLD_DIUCSR, 0x01 << 4); setbits8(cpld_base + CPLD_DIUCSR, CPLD_DIUCSR_BACKLIGHT); break; default: pr_err("%s: Unsupported monitor port %i\n", __func__, port); } iounmap(cpld_base); exit: of_node_put(cpld_node); }
static int __init cpm_uart_console_setup(struct console *co, char *options) { int baud = 38400; int bits = 8; int parity = 'n'; int flow = 'n'; int ret; struct uart_cpm_port *pinfo; struct uart_port *port; struct device_node *np = NULL; int i = 0; if (co->index >= UART_NR) { printk(KERN_ERR "cpm_uart: console index %d too high\n", co->index); return -ENODEV; } do { np = of_find_node_by_type(np, "serial"); if (!np) return -ENODEV; if (!of_device_is_compatible(np, "fsl,cpm1-smc-uart") && !of_device_is_compatible(np, "fsl,cpm1-scc-uart") && !of_device_is_compatible(np, "fsl,cpm2-smc-uart") && !of_device_is_compatible(np, "fsl,cpm2-scc-uart")) i--; } while (i++ != co->index); pinfo = &cpm_uart_ports[co->index]; pinfo->flags |= FLAG_CONSOLE; port = &pinfo->port; ret = cpm_uart_init_port(np, pinfo); of_node_put(np); if (ret) return ret; if (options) { uart_parse_options(options, &baud, &parity, &bits, &flow); } else { if ((baud = uart_baudrate()) == -1) baud = 9600; } #ifdef CONFIG_PPC_EARLY_DEBUG_CPM udbg_putc = NULL; #endif if (IS_SMC(pinfo)) { out_be16(&pinfo->smcup->smc_brkcr, 0); cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX); clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX | SMCM_TX); clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN); } else { out_be16(&pinfo->sccup->scc_brkcr, 0); cpm_line_cr_cmd(pinfo, CPM_CR_GRA_STOP_TX); clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX); clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT); } ret = cpm_uart_allocbuf(pinfo, 1); if (ret) return ret; cpm_uart_initbd(pinfo); if (IS_SMC(pinfo)) cpm_uart_init_smc(pinfo); else cpm_uart_init_scc(pinfo); uart_set_options(port, co, baud, parity, bits, flow); cpm_line_cr_cmd(pinfo, CPM_CR_RESTART_TX); return 0; }
static void __init mpc836x_mds_setup_arch(void) { struct device_node *np; u8 __iomem *bcsr_regs = NULL; if (ppc_md.progress) ppc_md.progress("mpc836x_mds_setup_arch()", 0); /* */ np = of_find_node_by_name(NULL, "bcsr"); if (np) { struct resource res; of_address_to_resource(np, 0, &res); bcsr_regs = ioremap(res.start, resource_size(&res)); of_node_put(np); } mpc83xx_setup_pci(); #ifdef CONFIG_QUICC_ENGINE qe_reset(); if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) { par_io_init(np); of_node_put(np); for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;) par_io_of_config(np); #ifdef CONFIG_QE_USB /* */ par_io_config_pin(1, 2, 1, 0, 3, 0); /* */ par_io_config_pin(1, 3, 1, 0, 3, 0); /* */ par_io_config_pin(1, 8, 1, 0, 1, 0); /* */ par_io_config_pin(1, 10, 2, 0, 3, 0); /* */ par_io_config_pin(1, 9, 2, 1, 3, 0); /* */ par_io_config_pin(1, 11, 2, 1, 3, 0); /* */ par_io_config_pin(2, 20, 2, 0, 1, 0); /* */ #endif /* */ } if ((np = of_find_compatible_node(NULL, "network", "ucc_geth")) != NULL){ uint svid; /* */ #define BCSR9_GETHRST 0x20 clrbits8(&bcsr_regs[9], BCSR9_GETHRST); udelay(1000); setbits8(&bcsr_regs[9], BCSR9_GETHRST); /* */ svid = mfspr(SPRN_SVR); if (svid == 0x80480021) { void __iomem *immap; immap = ioremap(get_immrbase() + 0x14a8, 8); /* */ setbits32(immap, 0x0c003000); /* */ clrsetbits_be32(immap + 4, 0xff0, 0xaa0); iounmap(immap); } iounmap(bcsr_regs); of_node_put(np); } #endif /* */ }
static void __init mpc85xx_mds_reset_ucc_phys(void) { struct device_node *np; static u8 __iomem *bcsr_regs; /* Map BCSR area */ np = of_find_node_by_name(NULL, "bcsr"); if (!np) return; bcsr_regs = of_iomap(np, 0); of_node_put(np); if (!bcsr_regs) return; if (machine_is(mpc8568_mds)) { #define BCSR_UCC1_GETH_EN (0x1 << 7) #define BCSR_UCC2_GETH_EN (0x1 << 7) #define BCSR_UCC1_MODE_MSK (0x3 << 4) #define BCSR_UCC2_MODE_MSK (0x3 << 0) /* Turn off UCC1 & UCC2 */ clrbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN); clrbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN); /* Mode is RGMII, all bits clear */ clrbits8(&bcsr_regs[11], BCSR_UCC1_MODE_MSK | BCSR_UCC2_MODE_MSK); /* Turn UCC1 & UCC2 on */ setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN); setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN); } else if (machine_is(mpc8569_mds)) { #define BCSR7_UCC12_GETHnRST (0x1 << 2) #define BCSR8_UEM_MARVELL_RST (0x1 << 1) #define BCSR_UCC_RGMII (0x1 << 6) #define BCSR_UCC_RTBI (0x1 << 5) /* * U-Boot mangles interrupt polarity for Marvell PHYs, * so reset built-in and UEM Marvell PHYs, this puts * the PHYs into their normal state. */ clrbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST); setbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST); setbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST); clrbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST); for (np = NULL; (np = of_find_compatible_node(np, "network", "ucc_geth")) != NULL;) { const unsigned int *prop; int ucc_num; prop = of_get_property(np, "cell-index", NULL); if (prop == NULL) continue; ucc_num = *prop - 1; prop = of_get_property(np, "phy-connection-type", NULL); if (prop == NULL) continue; if (strcmp("rtbi", (const char *)prop) == 0) clrsetbits_8(&bcsr_regs[7 + ucc_num], BCSR_UCC_RGMII, BCSR_UCC_RTBI); } } else if (machine_is(p1021_mds)) { #define BCSR11_ENET_MICRST (0x1 << 5) /* Reset Micrel PHY */ clrbits8(&bcsr_regs[11], BCSR11_ENET_MICRST); setbits8(&bcsr_regs[11], BCSR11_ENET_MICRST); } iounmap(bcsr_regs); }
static int mscan_set_mode(struct net_device *dev, u8 mode) { struct mscan_priv *priv = netdev_priv(dev); struct mscan_regs __iomem *regs = priv->reg_base; int ret = 0; int i; u8 canctl1; if (mode != MSCAN_NORMAL_MODE) { if (priv->tx_active) { /* Abort transfers before going to sleep */# out_8(®s->cantarq, priv->tx_active); /* Suppress TX done interrupts */ out_8(®s->cantier, 0); } canctl1 = in_8(®s->canctl1); if ((mode & MSCAN_SLPRQ) && !(canctl1 & MSCAN_SLPAK)) { setbits8(®s->canctl0, MSCAN_SLPRQ); for (i = 0; i < MSCAN_SET_MODE_RETRIES; i++) { if (in_8(®s->canctl1) & MSCAN_SLPAK) break; udelay(100); } /* * The mscan controller will fail to enter sleep mode, * while there are irregular activities on bus, like * somebody keeps retransmitting. This behavior is * undocumented and seems to differ between mscan built * in mpc5200b and mpc5200. We proceed in that case, * since otherwise the slprq will be kept set and the * controller will get stuck. NOTE: INITRQ or CSWAI * will abort all active transmit actions, if still * any, at once. */ if (i >= MSCAN_SET_MODE_RETRIES) netdev_dbg(dev, "device failed to enter sleep mode. " "We proceed anyhow.\n"); else priv->can.state = CAN_STATE_SLEEPING; } if ((mode & MSCAN_INITRQ) && !(canctl1 & MSCAN_INITAK)) { setbits8(®s->canctl0, MSCAN_INITRQ); for (i = 0; i < MSCAN_SET_MODE_RETRIES; i++) { if (in_8(®s->canctl1) & MSCAN_INITAK) break; } if (i >= MSCAN_SET_MODE_RETRIES) ret = -ENODEV; } if (!ret) priv->can.state = CAN_STATE_STOPPED; if (mode & MSCAN_CSWAI) setbits8(®s->canctl0, MSCAN_CSWAI); } else { canctl1 = in_8(®s->canctl1); if (canctl1 & (MSCAN_SLPAK | MSCAN_INITAK)) { clrbits8(®s->canctl0, MSCAN_SLPRQ | MSCAN_INITRQ); for (i = 0; i < MSCAN_SET_MODE_RETRIES; i++) { canctl1 = in_8(®s->canctl1); if (!(canctl1 & (MSCAN_INITAK | MSCAN_SLPAK))) break; } if (i >= MSCAN_SET_MODE_RETRIES) ret = -ENODEV; else priv->can.state = CAN_STATE_ERROR_ACTIVE; } } return ret; }
/** * mpc5200_psc_ac97_gpio_reset: Use gpio pins to reset the ac97 bus * * @psc: psc number to reset (only psc 1 and 2 support ac97) */ int mpc5200_psc_ac97_gpio_reset(int psc_number) { unsigned long flags; u32 gpio; u32 mux; int out; int reset; int sync; if ((!simple_gpio) || (!wkup_gpio)) return -ENODEV; switch (psc_number) { case 0: reset = PSC1_RESET; /* AC97_1_RES */ sync = PSC1_SYNC; /* AC97_1_SYNC */ out = PSC1_SDATA_OUT; /* AC97_1_SDATA_OUT */ gpio = MPC52xx_GPIO_PSC1_MASK; break; case 1: reset = PSC2_RESET; /* AC97_2_RES */ sync = PSC2_SYNC; /* AC97_2_SYNC */ out = PSC2_SDATA_OUT; /* AC97_2_SDATA_OUT */ gpio = MPC52xx_GPIO_PSC2_MASK; break; default: pr_err(__FILE__ ": Unable to determine PSC, no ac97 " "cold-reset will be performed\n"); return -ENODEV; } spin_lock_irqsave(&gpio_lock, flags); /* Reconfiure pin-muxing to gpio */ mux = in_be32(&simple_gpio->port_config); out_be32(&simple_gpio->port_config, mux & (~gpio)); /* enable gpio pins for output */ setbits8(&wkup_gpio->wkup_gpioe, reset); setbits32(&simple_gpio->simple_gpioe, sync | out); setbits8(&wkup_gpio->wkup_ddr, reset); setbits32(&simple_gpio->simple_ddr, sync | out); /* Assert cold reset */ clrbits32(&simple_gpio->simple_dvo, sync | out); clrbits8(&wkup_gpio->wkup_dvo, reset); /* wait for 1 us */ udelay(1); /* Deassert reset */ setbits8(&wkup_gpio->wkup_dvo, reset); /* wait at least 200ns */ /* 7 ~= (200ns * timebase) / ns2sec */ __delay(7); /* Restore pin-muxing */ out_be32(&simple_gpio->port_config, mux); spin_unlock_irqrestore(&gpio_lock, flags); return 0; }
/* ************************************************************************ * * Setup the architecture * */ static void __init mpc836x_mds_setup_arch(void) { struct device_node *np; u8 __iomem *bcsr_regs = NULL; if (ppc_md.progress) ppc_md.progress("mpc836x_mds_setup_arch()", 0); /* Map BCSR area */ np = of_find_node_by_name(NULL, "bcsr"); if (np) { struct resource res; of_address_to_resource(np, 0, &res); bcsr_regs = ioremap(res.start, resource_size(&res)); of_node_put(np); } #ifdef CONFIG_PCI for_each_compatible_node(np, "pci", "fsl,mpc8349-pci") mpc83xx_add_bridge(np); #endif #ifdef CONFIG_QUICC_ENGINE qe_reset(); if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) { par_io_init(np); of_node_put(np); for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;) par_io_of_config(np); #ifdef CONFIG_QE_USB /* Must fixup Par IO before QE GPIO chips are registered. */ par_io_config_pin(1, 2, 1, 0, 3, 0); /* USBOE */ par_io_config_pin(1, 3, 1, 0, 3, 0); /* USBTP */ par_io_config_pin(1, 8, 1, 0, 1, 0); /* USBTN */ par_io_config_pin(1, 10, 2, 0, 3, 0); /* USBRXD */ par_io_config_pin(1, 9, 2, 1, 3, 0); /* USBRP */ par_io_config_pin(1, 11, 2, 1, 3, 0); /* USBRN */ par_io_config_pin(2, 20, 2, 0, 1, 0); /* CLK21 */ #endif /* CONFIG_QE_USB */ } if ((np = of_find_compatible_node(NULL, "network", "ucc_geth")) != NULL){ uint svid; /* Reset the Ethernet PHY */ #define BCSR9_GETHRST 0x20 clrbits8(&bcsr_regs[9], BCSR9_GETHRST); udelay(1000); setbits8(&bcsr_regs[9], BCSR9_GETHRST); /* handle mpc8360ea rev.2.1 erratum 2: RGMII Timing */ svid = mfspr(SPRN_SVR); if (svid == 0x80480021) { void __iomem *immap; immap = ioremap(get_immrbase() + 0x14a8, 8); /* * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2) * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1) */ setbits32(immap, 0x0c003000); /* * IMMR + 0x14AC[20:27] = 10101010 * (data delay for both UCC's) */ clrsetbits_be32(immap + 4, 0xff0, 0xaa0); iounmap(immap); } iounmap(bcsr_regs); of_node_put(np); } #endif /* CONFIG_QUICC_ENGINE */ }
int mpc5200_psc_ac97_gpio_reset(int psc_number) { unsigned long flags; u32 gpio; u32 mux; int out; int reset; int sync; if ((!simple_gpio) || (!wkup_gpio)) return -ENODEV; switch (psc_number) { case 0: reset = PSC1_RESET; sync = PSC1_SYNC; out = PSC1_SDATA_OUT; gpio = MPC52xx_GPIO_PSC1_MASK; break; case 1: reset = PSC2_RESET; sync = PSC2_SYNC; out = PSC2_SDATA_OUT; gpio = MPC52xx_GPIO_PSC2_MASK; break; default: pr_err(__FILE__ ": Unable to determine PSC, no ac97 " "cold-reset will be performed\n"); return -ENODEV; } spin_lock_irqsave(&gpio_lock, flags); mux = in_be32(&simple_gpio->port_config); out_be32(&simple_gpio->port_config, mux & (~gpio)); setbits8(&wkup_gpio->wkup_gpioe, reset); setbits32(&simple_gpio->simple_gpioe, sync | out); setbits8(&wkup_gpio->wkup_ddr, reset); setbits32(&simple_gpio->simple_ddr, sync | out); clrbits32(&simple_gpio->simple_dvo, sync | out); clrbits8(&wkup_gpio->wkup_dvo, reset); udelay(1); setbits8(&wkup_gpio->wkup_dvo, reset); __delay(7); out_be32(&simple_gpio->port_config, mux); spin_unlock_irqrestore(&gpio_lock, flags); return 0; }