/** * fsl_ssi_hw_params - program the sample size * * Most of the SSI registers have been programmed in the startup function, * but the word length must be programmed here. Unfortunately, programming * the SxCCR.WL bits requires the SSI to be temporarily disabled. This can * cause a problem with supporting simultaneous playback and capture. If * the SSI is already playing a stream, then that stream may be temporarily * stopped when you start capture. * * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the * clock master. */ static int fsl_ssi_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai) { struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); if (substream == ssi_private->first_stream) { struct ccsr_ssi __iomem *ssi = ssi_private->ssi; unsigned int sample_size = snd_pcm_format_width(params_format(hw_params)); u32 wl = CCSR_SSI_SxCCR_WL(sample_size); /* The SSI should always be disabled at this points (SSIEN=0) */ /* In synchronous mode, the SSI uses STCCR for capture */ if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) || !ssi_private->asynchronous) clrsetbits_be32(&ssi->stccr, CCSR_SSI_SxCCR_WL_MASK, wl); else clrsetbits_be32(&ssi->srccr, CCSR_SSI_SxCCR_WL_MASK, wl); } return 0; }
static int fsl_ssi_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai) { struct fsl_ssi_private *ssi_private = cpu_dai->private_data; if (substream == ssi_private->first_stream) { struct ccsr_ssi __iomem *ssi = ssi_private->ssi; unsigned int sample_size = snd_pcm_format_width(params_format(hw_params)); u32 wl = CCSR_SSI_SxCCR_WL(sample_size); if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) || !ssi_private->asynchronous) clrsetbits_be32(&ssi->stccr, CCSR_SSI_SxCCR_WL_MASK, wl); else clrsetbits_be32(&ssi->srccr, CCSR_SSI_SxCCR_WL_MASK, wl); } return 0; }
int board_mmc_init(bd_t *bd) { struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR; if (!hwconfig("esdhc")) return 0; clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD); clrsetbits_be32(&im->sysconf.sicrh, SICRH_SPI, SICRH_SPI_SD); return fsl_esdhc_mmc_init(bd); }
int checkboard (void) { u32 val_gpdat, board_rev_gpio; volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); char board_rev = 0; struct cpu_type *cpu; val_gpdat = pgpio->gpdat; board_rev_gpio = val_gpdat & BOARDREV_MASK; if (board_rev_gpio == BOARDREV_C) board_rev = 'C'; else if (board_rev_gpio == BOARDREV_B) board_rev = 'B'; else panic ("Unexpected Board REV %x detected!!\n", board_rev_gpio); cpu = gd->cpu; printf ("Board: %sRDB Rev%c\n", cpu->name, board_rev); setbits_be32(&pgpio->gpdir, GPIO_DIR); /* * Bringing the following peripherals out of reset via GPIOs * 0 = reset and 1 = out of reset * GPIO12 - Reset to Ethernet Switch * GPIO13 - Reset to SLIC/SLAC devices * GPIO14 - Reset to SGMII_PHY_N * GPIO15 - Reset to PCIe slots * GPIO6 - Reset to RGMII PHY * GPIO5 - Reset to USB3300 devices 1 = reset and 0 = out of reset */ clrsetbits_be32(&pgpio->gpdat, USB_RST_CLR, BOARD_PERI_RST_SET); return 0; }
int qe_usb_clock_set(enum qe_clock clk, int rate) { struct qe_mux __iomem *mux = &qe_immr->qmx; unsigned long flags; u32 val; switch (clk) { case QE_CLK3: val = QE_CMXGCR_USBCS_CLK3; break; case QE_CLK5: val = QE_CMXGCR_USBCS_CLK5; break; case QE_CLK7: val = QE_CMXGCR_USBCS_CLK7; break; case QE_CLK9: val = QE_CMXGCR_USBCS_CLK9; break; case QE_CLK13: val = QE_CMXGCR_USBCS_CLK13; break; case QE_CLK17: val = QE_CMXGCR_USBCS_CLK17; break; case QE_CLK19: val = QE_CMXGCR_USBCS_CLK19; break; case QE_CLK21: val = QE_CMXGCR_USBCS_CLK21; break; case QE_BRG9: val = QE_CMXGCR_USBCS_BRG9; break; case QE_BRG10: val = QE_CMXGCR_USBCS_BRG10; break; default: pr_err("%s: requested unknown clock %d\n", __func__, clk); return -EINVAL; } if (qe_clock_is_brg(clk)) qe_setbrg(clk, rate, 1); spin_lock_irqsave(&cmxgcr_lock, flags); clrsetbits_be32(&mux->cmxgcr, QE_CMXGCR_USBCS, val); spin_unlock_irqrestore(&cmxgcr_lock, flags); return 0; }
void sdhci_be32bs_writeb(struct sdhci_host *host, u8 val, int reg) { int base = reg & ~0x3; int shift = (reg & 0x3) * 8; clrsetbits_be32(host->ioaddr + base , 0xff << shift, val << shift); }
/* * Set the DMACR register in the GUTS * * The DMACR register determines the source of initiated transfers for each * channel on each DMA controller. Rather than have a bunch of repetitive * macros for the bit patterns, we just have a function that calculates * them. * * guts: Pointer to GUTS structure * co: The DMA controller (0 or 1) * ch: The channel on the DMA controller (0, 1, 2, or 3) * device: The device to set as the target (CCSR_GUTS_DMUXCR_xxx) */ static inline void guts_set_dmuxcr(struct ccsr_guts_85xx __iomem *guts, unsigned int co, unsigned int ch, unsigned int device) { unsigned int shift = 16 + (8 * (1 - co) + 2 * (3 - ch)); clrsetbits_be32(&guts->dmuxcr, 3 << shift, device << shift); }
static void esdhc_writew(struct sdhci_host *host, u16 val, int reg) { struct sdhci_of_host *of_host = sdhci_priv(host); int base = reg & ~0x3; int shift = (reg & 0x2) * 8; switch (reg) { case SDHCI_TRANSFER_MODE: /* * Postpone this write, we must do it together with a * command write that is down below. */ of_host->xfer_mode_shadow = val; return; case SDHCI_COMMAND: esdhc_writel(host, val << 16 | of_host->xfer_mode_shadow, SDHCI_TRANSFER_MODE); return; case SDHCI_BLOCK_SIZE: /* * Two last DMA bits are reserved, and first one is used for * non-standard blksz of 4096 bytes that we don't support * yet. So clear the DMA boundary bits. */ val &= ~SDHCI_MAKE_BLKSZ(0x7, 0); /* fall through */ } clrsetbits_be32(host->ioaddr + base, 0xffff << shift, val << shift); }
/* * Miscellaneous late-boot configurations * * If a VSC7385 microcode image is present, then upload it. */ int misc_init_r(void) { #ifdef CONFIG_MPC8XXX_SPI immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; sysconf83xx_t *sysconf = &immr->sysconf; /* * Set proper bits in SICRH to allow SPI on header J8 * * NOTE: this breaks the TSEC2 interface, attached to the Vitesse * switch. The pinmux configuration does not have a fine enough * granularity to support both simultaneously. */ clrsetbits_be32(&sysconf->sicrh, SICRH_GPIO_A_TSEC2, SICRH_GPIO_A_GPIO); puts("WARNING: SPI enabled, TSEC2 support is broken\n"); /* Set header J8 SPI chip select output, disabled */ setbits_be32(&immr->gpio[0].dir, SPI_CS_MASK); setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK); #endif #ifdef CONFIG_VSC7385_IMAGE if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE, CONFIG_VSC7385_IMAGE_SIZE)) { puts("Failure uploading VSC7385 microcode.\n"); return 1; } #endif return 0; }
static void checkboard(void) { u32 val_gpdat, board_rev_gpio; void __iomem *gpio_regs = (void __iomem *)MPC85xx_GPIO_ADDR; val_gpdat = in_be32(gpio_regs + MPC85xx_GPIO_GPDAT); board_rev_gpio = val_gpdat & BOARDREV_MASK; if ((board_rev_gpio != BOARDREV_C) && (board_rev_gpio != BOARDREV_B) && (board_rev_gpio != BOARDREV_D)) panic("Unexpected Board REV %x detected!!\n", board_rev_gpio); setbits_be32((gpio_regs + MPC85xx_GPIO_GPDIR), GPIO_DIR); /* * Bringing the following peripherals out of reset via GPIOs * 0 = reset and 1 = out of reset * GPIO12 - Reset to Ethernet Switch * GPIO13 - Reset to SLIC/SLAC devices * GPIO14 - Reset to SGMII_PHY_N * GPIO15 - Reset to PCIe slots * GPIO6 - Reset to RGMII PHY * GPIO5 - Reset to USB3300 devices 1 = reset and 0 = out of reset */ clrsetbits_be32((gpio_regs + MPC85xx_GPIO_GPDAT), USB_RST_CLR, BOARD_PERI_RST_SET); }
int board_mmc_init(bd_t *bd) { struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR; char buffer[HWCONFIG_BUFFER_SIZE] = {0}; int esdhc_hwconfig_enabled = 0; if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0) esdhc_hwconfig_enabled = hwconfig_f("esdhc", buffer); if (esdhc_hwconfig_enabled == 0) return 0; clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD); clrsetbits_be32(&im->sysconf.sicrh, SICRH_SPI, SICRH_SPI_SD); return fsl_esdhc_mmc_init(bd); }
int board_mmc_init(bd_t *bd) { struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR; u8 *bcsr = (u8 *)CONFIG_SYS_BCSR; if (!hwconfig("esdhc")) return 0; /* Set SPI_SD, SER_SD, and IRQ4_WP so that SD signals go through */ bcsr[0xc] |= 0x4c; /* Set proper bits in SICR to allow SD signals through */ clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD); clrsetbits_be32(&im->sysconf.sicrh, SICRH_GPIO2_E | SICRH_SPI, SICRH_GPIO2_E_SD | SICRH_SPI_SD); return fsl_esdhc_mmc_init(bd); }
static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type) { struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; unsigned long gpio = irqd_to_hwirq(d); void __iomem *reg; unsigned int shift; unsigned long flags; if (gpio < 16) { reg = mm->regs + GPIO_ICR; shift = (15 - gpio) * 2; } else { reg = mm->regs + GPIO_ICR2; shift = (15 - (gpio % 16)) * 2; } switch (flow_type) { case IRQ_TYPE_EDGE_FALLING: case IRQ_TYPE_LEVEL_LOW: spin_lock_irqsave(&mpc8xxx_gc->lock, flags); clrsetbits_be32(reg, 3 << shift, 2 << shift); spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); break; case IRQ_TYPE_EDGE_RISING: case IRQ_TYPE_LEVEL_HIGH: spin_lock_irqsave(&mpc8xxx_gc->lock, flags); clrsetbits_be32(reg, 3 << shift, 1 << shift); spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); break; case IRQ_TYPE_EDGE_BOTH: spin_lock_irqsave(&mpc8xxx_gc->lock, flags); clrbits32(reg, 3 << shift); spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); break; default: return -EINVAL; } return 0; }
static void mpc837x_rdb_sd_cfg(void) { void __iomem *im; im = ioremap(get_immrbase(), 0x1000); if (!im) { WARN_ON(1); return; } /* * On RDB boards (in contrast to MDS) USBB pins are used for SD only, * so we can safely mux them away from the USB block. */ clrsetbits_be32(im + MPC83XX_SICRL_OFFS, MPC837X_SICRL_USBB_MASK, MPC837X_SICRL_SD); clrsetbits_be32(im + MPC83XX_SICRH_OFFS, MPC837X_SICRH_SPI_MASK, MPC837X_SICRH_SD); iounmap(im); }
void iopin_initialize_bits(iopin_t *ioregs_init, int len) { short i, j, p; u32 *reg, mask; immap_t *im = (immap_t *)CONFIG_SYS_IMMR; reg = (u32 *)&(im->io_ctrl); /* iterate over table entries */ for (i = 0; i < len; i++) { /* iterate over pins within a table entry */ for (p = 0, j = ioregs_init[i].p_offset / sizeof(u_long); p < ioregs_init[i].nr_pins; p++, j++) { if (ioregs_init[i].bit_or & IO_PIN_OVER_EACH) { /* replace all settings at once */ out_be32(reg + j, ioregs_init[i].val); } else { /* * only replace individual parts, but * REPLACE them instead of just ORing * them in and "inheriting" previously * set bits which we don't want */ mask = 0; if (ioregs_init[i].bit_or & IO_PIN_OVER_FMUX) mask |= IO_PIN_FMUX(3); if (ioregs_init[i].bit_or & IO_PIN_OVER_HOLD) mask |= IO_PIN_HOLD(3); if (ioregs_init[i].bit_or & IO_PIN_OVER_PULL) mask |= IO_PIN_PUD(1) | IO_PIN_PUE(1); if (ioregs_init[i].bit_or & IO_PIN_OVER_STRIG) mask |= IO_PIN_ST(1); if (ioregs_init[i].bit_or & IO_PIN_OVER_DRVSTR) mask |= IO_PIN_DS(3); /* * DON'T do the "mask, then insert" * in place on the register, it may * break access to external hardware * (like boot ROMs) when configuring * LPB related pins, while the code to * configure the pin is read from this * very address region */ clrsetbits_be32(reg + j, mask, ioregs_init[i].val & mask); } } } }
int mpc837x_usb_cfg(void) { void __iomem *immap; struct device_node *np = NULL; const void *prop; const void *dr_mode = NULL; /* 2011.2.28, added by panasonic ---> */ int ret = 0; np = of_find_compatible_node(NULL, NULL, "fsl-usb2-dr"); if (!np) return -ENODEV; prop = of_get_property(np, "phy_type", NULL); if (!prop || (strcmp(prop, "ulpi") && strcmp(prop, "serial"))) { printk(KERN_WARNING "837x USB PHY type not supported\n"); of_node_put(np); return -EINVAL; } dr_mode = of_get_property(np, "dr_mode", NULL); /* 2011.2.28, added by panasonic */ /* Map IMMR space for pin and clock settings */ immap = ioremap(get_immrbase(), 0x1000); if (!immap) { of_node_put(np); return -ENOMEM; } /* Configure clock */ clrsetbits_be32(immap + MPC83XX_SCCR_OFFS, MPC837X_SCCR_USB_DRCM_11, (!dr_mode||strcmp(dr_mode,"none"))? MPC837X_SCCR_USB_DRCM_11: 0);/* 2011.2.28, modified by panasonic (SAV) */ /* Configure pin mux for ULPI/serial */ clrsetbits_be32(immap + MPC83XX_SICRL_OFFS, MPC837X_SICRL_USB_MASK, MPC837X_SICRL_USB_ULPI); iounmap(immap); of_node_put(np); return ret; }
int board_mmc_init(bd_t *bd) { struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_MPC85xx_GUTS_ADDR; u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE; u8 bcsr6 = BCSR6_SD_CARD_1BIT; if (!hwconfig("esdhc")) return 0; printf("Enabling eSDHC...\n" " For eSDHC to function, I2C2 "); if (esdhc_disables_uart0()) { printf("and UART0 should be disabled.\n"); printf(" Redirecting stderr, stdout and stdin to UART1...\n"); console_assign(stderr, "eserial1"); console_assign(stdout, "eserial1"); console_assign(stdin, "eserial1"); printf("Switched to UART1 (initial log has been printed to " "UART0).\n"); clrsetbits_be32(&gur->plppar1, PLPPAR1_UART0_BIT_MASK, PLPPAR1_ESDHC_4BITS_VAL); clrsetbits_be32(&gur->plpdir1, PLPDIR1_UART0_BIT_MASK, PLPDIR1_ESDHC_4BITS_VAL); bcsr6 |= BCSR6_SD_CARD_4BITS; } else { printf("should be disabled.\n"); } /* Assign I2C2 signals to eSDHC. */ clrsetbits_be32(&gur->plppar1, PLPPAR1_I2C_BIT_MASK, PLPPAR1_ESDHC_VAL); clrsetbits_be32(&gur->plpdir1, PLPDIR1_I2C_BIT_MASK, PLPDIR1_ESDHC_VAL); /* Mux I2C2 (and optionally UART0) signals to eSDHC. */ setbits_8(&bcsr[6], bcsr6); return fsl_esdhc_mmc_init(bd); }
int board_early_init_r(void) { struct km_bec_fpga *base = (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE; #if defined(CONFIG_SUVD3) immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; fsl_lbc_t *lbc = &immap->im_lbc; u32 *mxmr = &lbc->mamr; #endif #if defined(CONFIG_MPC8360) unsigned short svid; /* * Because of errata in the UCCs, we have to write to the reserved * registers to slow the clocks down. */ svid = SVR_REV(mfspr(SVR)); switch (svid) { case 0x0020: /* * MPC8360ECE.pdf QE_ENET10 table 4: * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2) * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1) */ setbits_be32((void *)(CONFIG_SYS_IMMR + 0x14a8), 0x0c003000); break; case 0x0021: /* * MPC8360ECE.pdf QE_ENET10 table 4: * IMMR + 0x14AC[24:27] = 1010 */ clrsetbits_be32((void *)(CONFIG_SYS_IMMR + 0x14ac), 0x00000050, 0x000000a0); break; } #endif /* enable the PHY on the PIGGY */ setbits_8(&base->pgy_eth, 0x01); /* enable the Unit LED (green) */ setbits_8(&base->oprth, WRL_BOOT); /* enable Application Buffer */ setbits_8(&base->oprtl, OPRTL_XBUFENA); #if defined(CONFIG_SUVD3) /* configure UPMA for APP1 */ upmconfig(UPMA, (uint *) upma_table, sizeof(upma_table) / sizeof(uint)); out_be32(mxmr, CONFIG_SYS_MAMR); #endif return 0; }
/** * fsl_ssi_prepare: prepare the SSI. * * Most of the SSI registers have been programmed in the startup function, * but the word length must be programmed here. Unfortunately, programming * the SxCCR.WL bits requires the SSI to be temporarily disabled. This can * cause a problem with supporting simultaneous playback and capture. If * the SSI is already playing a stream, then that stream may be temporarily * stopped when you start capture. * * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the * clock master. */ static int fsl_ssi_prepare(struct snd_pcm_substream *substream) { struct snd_pcm_runtime *runtime = substream->runtime; struct snd_soc_pcm_runtime *rtd = substream->private_data; struct fsl_ssi_private *ssi_private = rtd->dai->cpu_dai->private_data; struct ccsr_ssi __iomem *ssi = ssi_private->ssi; u32 wl; wl = CCSR_SSI_SxCCR_WL(snd_pcm_format_width(runtime->format)); clrbits32(&ssi->scr, CCSR_SSI_SCR_SSIEN); if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) clrsetbits_be32(&ssi->stccr, CCSR_SSI_SxCCR_WL_MASK, wl); else clrsetbits_be32(&ssi->srccr, CCSR_SSI_SxCCR_WL_MASK, wl); setbits32(&ssi->scr, CCSR_SSI_SCR_SSIEN); return 0; }
/* * write into UPMB ram */ static void upmb_write (u_char addr, ulong val) { volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); out_be32 (&lbc->mdr, val); clrsetbits_be32(&lbc->mbmr, MxMR_MAD_MSK, MxMR_OP_WARR | (addr & MxMR_MAD_MSK)); /* dummy access to perform write */ out_8 ((void __iomem *)CONFIG_SYS_NAND0_BASE, 0); clrbits_be32(&lbc->mbmr, MxMR_OP_WARR); }
int ucc_set_qe_mux_mii_mng(unsigned int ucc_num) { unsigned long flags; if (ucc_num > UCC_MAX_NUM - 1) return -EINVAL; spin_lock_irqsave(&cmxgcr_lock, flags); clrsetbits_be32(&qe_immr->qmx.cmxgcr, QE_CMXGCR_MII_ENET_MNG, ucc_num << QE_CMXGCR_MII_ENET_MNG_SHIFT); spin_unlock_irqrestore(&cmxgcr_lock, flags); return 0; }
static int bcm6358_usbh_init(struct phy *phy) { struct bcm6358_usbh_priv *priv = dev_get_priv(phy->dev); /* configure to work in native cpu endian */ clrsetbits_be32(priv->regs + USBH_SWAP_REG, USBH_SWAP_EHCI_ENDIAN | USBH_SWAP_OHCI_ENDIAN, USBH_SWAP_EHCI_DATA | USBH_SWAP_OHCI_DATA); /* test port control */ writel_be(USBH_TEST_PORT_CTL, priv->regs + USBH_TEST_REG); return 0; }
int mpc837x_usb_cfg(void) { void __iomem *immap; struct device_node *np = NULL; const void *prop; int ret = 0; np = of_find_compatible_node(NULL, NULL, "fsl-usb2-dr"); if (!np || !of_device_is_available(np)) return -ENODEV; prop = of_get_property(np, "phy_type", NULL); if (!prop || (strcmp(prop, "ulpi") && strcmp(prop, "serial"))) { printk(KERN_WARNING "837x USB PHY type not supported\n"); of_node_put(np); return -EINVAL; } immap = ioremap(get_immrbase(), 0x1000); if (!immap) { of_node_put(np); return -ENOMEM; } clrsetbits_be32(immap + MPC83XX_SCCR_OFFS, MPC837X_SCCR_USB_DRCM_11, MPC837X_SCCR_USB_DRCM_11); clrsetbits_be32(immap + MPC83XX_SICRL_OFFS, MPC837X_SICRL_USB_MASK, MPC837X_SICRL_USB_ULPI); iounmap(immap); of_node_put(np); return ret; }
/* * Initialize UPMC RAM */ static void upmc_write (u_char addr, uint val) { volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; out_be32 (&lbc->mdr, val); clrsetbits_be32(&lbc->mcmr, MxMR_MAD_MSK, MxMR_OP_WARR | (addr & MxMR_MAD_MSK)); /* dummy access to perform write */ out_8 ((void __iomem *)CONFIG_SYS_CAN_BASE, 0); /* normal operation */ clrbits_be32(&lbc->mcmr, MxMR_OP_WARR); }
/** * fsl_ssi_hw_params - program the sample size * * Most of the SSI registers have been programmed in the startup function, * but the word length must be programmed here. Unfortunately, programming * the SxCCR.WL bits requires the SSI to be temporarily disabled. This can * cause a problem with supporting simultaneous playback and capture. If * the SSI is already playing a stream, then that stream may be temporarily * stopped when you start capture. * * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the * clock master. */ static int fsl_ssi_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai) { struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); struct ccsr_ssi __iomem *ssi = ssi_private->ssi; unsigned int sample_size = snd_pcm_format_width(params_format(hw_params)); u32 wl = CCSR_SSI_SxCCR_WL(sample_size); int enabled = in_be32(&ssi->scr) & CCSR_SSI_SCR_SSIEN; /* * If we're in synchronous mode, and the SSI is already enabled, * then STCCR is already set properly. */ if (enabled && ssi_private->cpu_dai_drv.symmetric_rates) return 0; /* * FIXME: The documentation says that SxCCR[WL] should not be * modified while the SSI is enabled. The only time this can * happen is if we're trying to do simultaneous playback and * capture in asynchronous mode. Unfortunately, I have been enable * to get that to work at all on the P1022DS. Therefore, we don't * bother to disable/enable the SSI when setting SxCCR[WL], because * the SSI will stop anyway. Maybe one day, this will get fixed. */ /* In synchronous mode, the SSI uses STCCR for capture */ if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) || ssi_private->cpu_dai_drv.symmetric_rates) clrsetbits_be32(&ssi->stccr, CCSR_SSI_SxCCR_WL_MASK, wl); else clrsetbits_be32(&ssi->srccr, CCSR_SSI_SxCCR_WL_MASK, wl); return 0; }
static int fsl_lbc_ctrl_init(struct fsl_lbc_ctrl *ctrl, struct device_node *node) { struct fsl_lbc_regs __iomem *lbc = ctrl->regs; /* clear event registers */ setbits32(&lbc->ltesr, LTESR_CLEAR); out_be32(&lbc->lteatr, 0); out_be32(&lbc->ltear, 0); out_be32(&lbc->lteccr, LTECCR_CLEAR); out_be32(&lbc->ltedr, LTEDR_ENABLE); /* Set the monitor timeout value to the maximum for erratum A001 */ if (of_device_is_compatible(node, "fsl,elbc")) clrsetbits_be32(&lbc->lbcr, LBCR_BMT, LBCR_BMTPS); return 0; }
int board_early_init_f(void) { ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42); setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS); clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_RTS_B0_GPIO43); setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK | MPC85xx_PMUXCR2_UART_CTS_B1_SIM_PD); setbits_be32(&gur->halt_req_mask, HALTED_TO_HALT_REQ_MASK_0); clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_IFC_AD_GPIO_MASK | MPC85xx_PMUXCR_IFC_AD17_GPO_MASK, MPC85xx_PMUXCR_IFC_AD_GPIO | MPC85xx_PMUXCR_IFC_AD17_GPO | MPC85xx_PMUXCR_SDHC_USIM); return 0; }
int platform_diu_init(unsigned int xres, unsigned int yres, const char *port) { ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); u32 pixel_format; pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) | (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) | (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) | (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) | (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT)); printf("DIU: Switching to %ux%u\n", xres, yres); /* Set PMUXCR to switch the muxed pins from the LBC to the DIU */ clrsetbits_be32(&gur->pmuxcr, PMUXCR_ELBCDIU_MASK, PMUXCR_ELBCDIU_DIU); pmuxcr = in_be32(&gur->pmuxcr); return fsl_diu_init(xres, yres, pixel_format, 0); }
/** * fsl_ssi_prepare: prepare the SSI. * * Most of the SSI registers have been programmed in the startup function, * but the word length must be programmed here. Unfortunately, programming * the SxCCR.WL bits requires the SSI to be temporarily disabled. This can * cause a problem with supporting simultaneous playback and capture. If * the SSI is already playing a stream, then that stream may be temporarily * stopped when you start capture. * * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the * clock master. */ static int fsl_ssi_prepare(struct snd_pcm_substream *substream) { struct snd_pcm_runtime *runtime = substream->runtime; struct snd_soc_pcm_runtime *rtd = substream->private_data; struct fsl_ssi_private *ssi_private = rtd->dai->cpu_dai->private_data; struct ccsr_ssi __iomem *ssi = ssi_private->ssi; if (substream == ssi_private->first_stream) { u32 wl; /* The SSI should always be disabled at this points (SSIEN=0) */ wl = CCSR_SSI_SxCCR_WL(snd_pcm_format_width(runtime->format)); /* In synchronous mode, the SSI uses STCCR for capture */ clrsetbits_be32(&ssi->stccr, CCSR_SSI_SxCCR_WL_MASK, wl); } return 0; }
void sdhci_be32bs_writew(struct sdhci_host *host, u16 val, int reg) { struct sdhci_of_host *of_host = sdhci_priv(host); int base = reg & ~0x3; int shift = (reg & 0x2) * 8; switch (reg) { case SDHCI_TRANSFER_MODE: /* * Postpone this write, we must do it together with a * command write that is down below. */ of_host->xfer_mode_shadow = val; return; case SDHCI_COMMAND: sdhci_be32bs_writel(host, val << 16 | of_host->xfer_mode_shadow, SDHCI_TRANSFER_MODE); return; } clrsetbits_be32(host->ioaddr + base, 0xffff << shift, val << shift); }