static int hisi_offlinecompser_panel_off(struct platform_device *pdev)
{
int ret = 0;
struct hisi_fb_data_type *hisifd = NULL;
int i = 0;
BUG_ON(pdev == NULL);
hisifd = platform_get_drvdata(pdev);
BUG_ON(hisifd == NULL);
HISI_FB_DEBUG("index=%d, enter!\n", hisifd->index);
for (i = 0; i < HISI_DSS_OFFLINE_MAX_NUM; i++) {
char __iomem *ctl_base = hisifd->dss_base + DSS_GLB_WBE1_CH0_CTL +
i * (DSS_GLB_WBE1_CH1_CTL - DSS_GLB_WBE1_CH0_CTL);
cmdlist_config_stop(hisifd, i);
hisifd->offline_wb_status[i] = e_status_idle;
set_reg(ctl_base, 0x1, 1, 8);
set_reg(ctl_base, 0x0, 1, 8);
}
HISI_FB_DEBUG("index=%d, exit!\n", hisifd->index);
return ret;
}
static void offline_fail_proccess(struct k3_fb_data_type *k3fd, u32 wbe_chn, int block_num)
{
dss_overlay_t *pov_req = NULL;
char __iomem *dss_base = NULL;
u32 i = 0;
u32 ready = 0;
BUG_ON(k3fd == NULL);
pov_req = &(k3fd->ov_req);
BUG_ON(wbe_chn >= K3_DSS_OFFLINE_MAX_NUM);
BUG_ON(pov_req == NULL);
dss_base = k3fd->dss_base;
if(g_debug_ovl_offline_composer == 1) {
u32 test1 = inp32(k3fd->dss_base + DSS_CMD_LIST_OFFSET +CMDLIST_CH5_STATUS);
K3_FB_ERR("offline fail cmdlist status:0x%x\n", test1);
cmdlist_print_all_node(&k3fd->offline_cmdlist_head[wbe_chn]);
}
/*single channel fail.*/
cmdlist_config_stop(k3fd, wbe_chn);
for (i = 0; i < block_num; i++) {
char __iomem *ctl_base = k3fd->dss_base + DSS_GLB_WBE1_CH0_CTL +
wbe_chn * (DSS_GLB_WBE1_CH1_CTL - DSS_GLB_WBE1_CH0_CTL);
if(inp32(dss_base + DSS_GLB_GLB_STATUS) & (0x1 << (2+wbe_chn))) {
set_reg(ctl_base, 0x1, 1, 8);
set_reg(ctl_base, 0x0, 1, 8);
udelay(10);
}
set_reg(ctl_base, 0x1, 1, 8);
set_reg(ctl_base, 0x0, 1, 8);
}
for (i = 0; i < pov_req->layer_nums; i++) {
int chn_idx = pov_req->layer_infos[i].chn_idx - DPE2_CHN0;
int rot_idx = 0;
if(chn_idx > DPE3_CHN3 - DPE2_CHN0 || chn_idx < 0){
K3_FB_ERR("offline_add_virtual_frame chn:%d err\n", pov_req->layer_infos[i].chn_idx);
return;
}
set_reg(dss_base +DSS_GLB_DPE2_CH0_CTL + chn_idx * 0x04, 0, 32, 0);
if(isYUVPlanar(pov_req->layer_infos[i].src.format))
set_reg(dss_base +DSS_GLB_DPE2_CH0_CTL + (chn_idx + 1) * 0x04, 0, 32, 0);
rot_idx = k3_get_rot_index(pov_req->layer_infos[i].chn_idx);
if(rot_idx > 0){
set_reg(dss_base + DSS_GLB_ROT_TLB0_SCENE + rot_idx * 4, 0, 32, 0);
}
}
set_reg(dss_base + g_dss_module_base[pov_req->wb_layer_info.chn_idx][MODULE_DMA0]
+ WDMA_CTRL, 0, 1, 25);
if(pov_req->wb_layer_info.dst.mmu_enable)
set_reg(dss_base + g_dss_module_base[pov_req->wb_layer_info.chn_idx][MODULE_MMU_DMA0], 0, 1, 0);
if(pov_req->wb_layer_info.chn_idx == WBE1_CHN1){
set_reg(dss_base +DSS_GLB_OV2_SCENE, 0, 32, 0);
}
//start
set_reg(dss_base + DSS_GLB_OFFLINE_S2_CPU_IRQ_CLR, 0x44 << wbe_chn, 32, 0);
set_reg(dss_base + DSS_GLB_ADP_OFFLINE_START0 + wbe_chn * 0x04, 0x1, 32, 0);
// wait start irq
ready = 0;
i=0;
do {
udelay(10);
i++;
if(inp32(dss_base + DSS_GLB_OFFLINE_S2_CPU_IRQ_RAWSTAT) & BIT(2 + wbe_chn))
ready = 1;
} while((!ready) & (i < 100));
if(!ready) {
K3_FB_ERR("offline wait start irq timeout:0x%x,i=%d\n",
inp32(dss_base + DSS_GLB_OFFLINE_S2_CPU_IRQ_RAWSTAT), i);
if(g_debug_ovl_offline_composer > 0)
BUG_ON(1);
}
k3fd->offline_wb_status[wbe_chn] = e_status_idle;
return;
}
