void
cpu_configure(void)
{
irq_init();
config_rootfound("cpu", NULL);
config_rootfound("arcvideo", NULL);
config_rootfound("iobus", NULL);
spl0();
fiq_on();
}
/*
* Do general device autoconfiguration,
* then choose root device (etc.)
* Called by sys/kern/subr_autoconf.c: configure()
*/
void
cpu_configure(void)
{
/*
* Consider stopping for a debugger before
* autoconfiguration.
*/
if (boothowto & RB_KDB) {
#ifdef KGDB
/* XXX - Ask on console for kgdb_dev? */
/* Note: this will just return if kgdb_dev==NODEV */
kgdb_connect(1);
#else /* KGDB */
/* Either DDB or no debugger (just PROM). */
Debugger();
#endif /* KGDB */
}
/* General device autoconfiguration. */
if (config_rootfound("mainbus", NULL) == NULL)
panic("%s: mainbus not found", __func__);
/*
* Now that device autoconfiguration is finished,
* we can safely enable interrupts.
*/
printf("enabling interrupts\n");
(void)spl0();
}
void
cpu_configure(void)
{
footbridge_intr_evcnt_attach();
/*
* Since various PCI interrupts could be routed via the ICU
* (for PCI devices in the bridge) we need to set up the ICU
* now so that these interrupts can be established correctly
* i.e. This is a hack.
*/
isa_intr_init();
config_rootfound("mainbus", NULL);
#if defined(DEBUG)
/* Debugging information */
printf("ipl_bio=%08x ipl_net=%08x ipl_tty=%08x ipl_vm=%08x\n",
footbridge_imask[IPL_BIO], footbridge_imask[IPL_NET],
footbridge_imask[IPL_TTY], footbridge_imask[IPL_VM]);
printf("ipl_audio=%08x ipl_imp=%08x ipl_high=%08x ipl_serial=%08x\n",
footbridge_imask[IPL_AUDIO], footbridge_imask[IPL_CLOCK],
footbridge_imask[IPL_HIGH], footbridge_imask[IPL_SERIAL]);
#endif /* defined(DEBUG) */
/* Time to start taking interrupts so lets open the flood gates .... */
(void)spl0();
}
/*
* void cpu_configure()
*
* Configure all the root devices
* The root devices are expected to configure their own children
*/
void
cpu_configure(void)
{
config_hook_init();
/*
* Configure all the roots.
* We have to have a mainbus
*/
#if 0
startrtclock();
#endif
/*
* Since the ICU is not standard on the ARM we don't know
* if we have one until we find a bridge.
* Since various PCI interrupts could be routed via the ICU
* (for PCI devices in the bridge) we need to set up the ICU
* now so that these interrupts can be established correctly
* i.e. This is a hack.
*/
if (config_rootfound("mainbus", NULL) == NULL)
panic("configure: mainbus not configured");
/* Debugging information */
#ifdef DIAGNOSTIC
dump_spl_masks();
#endif
/* Time to start taking interrupts so lets open the flood gates .... */
(void)spl0();
}
/*
* Determine i/o configuration for a machine.
*/
void
cpu_configure(void)
{
startrtclock();
#if NBIOS32 > 0
bios32_init();
platform_init();
#endif
x86_64_proc0_tss_ldt_init();
if (config_rootfound("mainbus", NULL) == NULL)
panic("configure: mainbus not configured");
#ifdef INTRDEBUG
intr_printconfig();
#endif
#if NIOAPIC > 0
ioapic_enable();
#endif
#ifdef MULTIPROCESSOR
cpu_init_idle_lwps();
#endif
spl0();
lcr8(0);
}
void
configure()
{
extern int boothowto;
if (config_rootfound("backplane", NULL) == NULL)
panic("backplane not configured");
#if GENERIC
if ((boothowto & RB_ASKNAME) == 0)
setroot();
setconf();
#else
setroot();
#endif
/*
* Configure swap area and related system
* parameter based on device(s) used.
*/
swapconf();
dumpconf();
cold = 0;
mtpr(GC_CCF, PR_TXDB); /* Clear cold start flag in cpu */
}
/*
* Configure all devices found that we know about.
* This is done at boot time.
*/
void
cpu_configure(void)
{
#ifdef ENABLE_INT5_STATCLOCK
evcnt_attach_static(&statclock_ev);
#endif
(void)splhigh(); /* To be really sure.. */
if (config_rootfound("mainbus", NULL) == NULL)
panic("no mainbus found");
/* Configuration is finished, turn on interrupts. */
#ifdef ENABLE_INT5_STATCLOCK
/*
* Enable interrupt sources.
* We can't enable CPU INT5 which is used by statclock(9) here
* until cpu_initclocks(9) is called because there is no way
* to disable it other than setting status register by spl(9).
*/
_spllower(MIPS_INT_MASK_5);
#else
/* enable all source forcing SOFT_INTs cleared */
_splnone();
#endif
}
/*
* Determine mass storage and memory configuration for a machine.
* We get the PROM's root device and make sure we understand it, then
* attach it as `mainbus0'. We also set up to handle the PROM `sync'
* command.
*/
void
cpu_configure(void)
{
if (CPU_ISSUN4V)
mdesc_init();
bool userconf = (boothowto & RB_USERCONF) != 0;
/* fetch boot device settings */
get_bootpath_from_prom();
if (((boothowto & RB_USERCONF) != 0) && !userconf)
/*
* Old bootloaders do not pass boothowto, and MI code
* has already handled userconfig before we get here
* and finally fetch the right options. So if we missed
* it, just do it here.
*/
userconf_prompt();
/* block clock interrupts and anything below */
splclock();
/* Enable device interrupts */
setpstate(getpstate()|PSTATE_IE);
if (config_rootfound("mainbus", NULL) == NULL)
panic("mainbus not configured");
/* Enable device interrupts */
setpstate(getpstate()|PSTATE_IE);
(void)spl0();
}
void
cpu_configure(void)
{
if (config_rootfound("mainbus", NULL) == NULL)
panic("configure: mainbus not configured");
spl0();
}
void
cpu_configure(void)
{
splhigh();
if (config_rootfound("mainbus", NULL) == NULL)
panic("no mainbus found");
}
/*
* Configure all devices found that we know about.
* This is done at boot time.
*/
void
cpu_configure()
{
(void)splhigh(); /* To be really sure.. */
if (config_rootfound("mainbus", "mainbus") == NULL)
panic("no mainbus found");
/* Configuration is finished, turn on interrupts. */
_splnone(); /* enable all source forcing SOFT_INTs cleared */
}
void
cpu_configure(void)
{
(void)splhigh();
if (config_rootfound("zbbus", NULL) == NULL)
panic("no zbbus found");
_splnone();
}
/*
* called at boot time, configure all devices on system
*/
void
cpu_configure(void)
{
atari_realconfig = 1;
init_sicallback();
if (config_rootfound("mainbus", __UNCONST("mainbus")) == NULL)
panic("no mainbus found");
}
/*
* Configure all devices on system
*/
void
cpu_configure(void)
{
intr_init();
/* Kick off autoconfiguration. */
(void)splhigh();
if (config_rootfound("mainbus", "mainbus") == NULL)
panic("no mainbus found");
(void)spl0();
}
/*
* Configure all devices found that we know about.
* This is done at boot time.
*/
void
cpu_configure()
{
(void)splhigh(); /* To be really sure.. */
softintr_init();
if (config_rootfound("mainbus", "mainbus") == 0)
panic("no mainbus found");
(void)spl0();
cold = 0;
}
/*
* cpu_configure:
* called at boot time, configure all devices on the system
*/
void
cpu_configure(void)
{
mrg_init(); /* Init Mac ROM Glue */
startrtclock(); /* start before ADB attached */
if (config_rootfound("mainbus", NULL) == NULL)
panic("No mainbus found!");
(void)spl0();
}
/*
* Determine mass storage and memory configuration for a machine.
*/
void
cpu_configure()
{
booted_device = NULL; /* set by device drivers (if found) */
(void)splhigh();
isrinit();
if (config_rootfound("mainbus", NULL) == NULL)
panic("autoconfig failed, no root");
spl0();
}
void
cpu_configure()
{
/* Start configuration */
splhigh();
if (config_rootfound("mainbus", NULL) == NULL)
panic("no mainbus found");
/* Configuration is finished, turn on interrupts. */
spl0();
}
/*
* called at boot time, configure all devices on system
*/
void
configure()
{
int s;
#ifdef DEBUG_KERNEL_START
int i;
#endif
/*
* this is the real thing baby (i.e. not console init)
*/
amiga_realconfig = 1;
#ifdef DRACO
if (is_draco()) {
*draco_intena &= ~DRIRQ_GLOBAL;
} else
#endif
custom.intena = INTF_INTEN;
s = splhigh();
if (config_rootfound("mainbus", "mainbus") == NULL)
panic("no mainbus found");
#ifdef DEBUG_KERNEL_START
printf("survived autoconf, going to enable interrupts\n");
#endif
#ifdef DRACO
if (is_draco()) {
*draco_intena |= DRIRQ_GLOBAL;
/* softints always enabled */
} else
#endif
{
custom.intena = INTF_SETCLR | INTF_INTEN;
/* also enable hardware aided software interrupts */
custom.intena = INTF_SETCLR | INTF_SOFTINT;
}
#ifdef DEBUG_KERNEL_START
for (i=splhigh(); i>=s ;i-=0x100) {
splx(i);
printf("%d...", (i>>8) & 7);
}
printf("survived interrupt enable\n");
#else
splx(s);
#endif
cold = 0;
#ifdef DEBUG_KERNEL_START
printf("survived configure...\n");
#endif
}
/*
* Determine mass storage and memory configuration for a machine.
*/
void
cpu_configure(void)
{
booted_device = NULL; /* set by device drivers (if found) */
/* Initialise interrupt handlers */
isrinit();
if (config_rootfound("mainbus", NULL) == NULL)
panic("autoconfig failed, no root");
}
/*
* Walk the OFW device tree and configure found devices.
*
* Move this into common OFW module? -JJK
*/
void
ofrootfound(void)
{
int node;
struct ofbus_attach_args aa;
if (!(node = OF_peer(0)))
panic("No OFW root");
aa.oba_busname = "ofw";
aa.oba_phandle = node;
if (!config_rootfound("ofbus", &aa))
panic("ofw root ofbus not configured");
}
/*
* Configure all devices found that we know about.
* This is done at boot time.
*/
void
cpu_configure()
{
(void)splhigh(); /* Set mask to what we intend. */
if (config_rootfound("mainbus", "mainbus") == 0) {
panic("no mainbus found");
}
splinit(); /* Initialized, fire up interrupt system */
md_diskconf = disk_configure;
cold = 0;
}
void
cpu_configure(void)
{
calc_delayconst();
if (config_rootfound("elb", NULL) == NULL)
panic("configure: elb not configured");
printf("biomask %x netmask %x ttymask %x\n",
imask[IPL_BIO], imask[IPL_NET], imask[IPL_TTY]);
(void)spl0();
}
/*
* Determine i/o configuration for a machine.
*/
void
cpu_configure(void)
{
#if NBIOS32 > 0
bios32_init();
#endif
x86_64_proc0_tss_ldt_init();
if (config_rootfound("mainbus", NULL) == NULL)
panic("configure: mainbus not configured");
intr_printconfig();
#if NIOAPIC > 0
lapic_set_lvt();
ioapic_enable();
#endif
#ifdef MULTIPROCESSOR
cpu_init_idle_pcbs();
#endif
lcr8(0);
spl0();
cold = 0;
/*
* At this point the RNG is running, and if FSXR is set we can
* use it. Here we setup a periodic timeout to collect the data.
*/
if (viac3_rnd_present) {
timeout_set(&viac3_rnd_tmo, viac3_rnd, &viac3_rnd_tmo);
viac3_rnd(&viac3_rnd_tmo);
}
if (has_rdrand) {
timeout_set(&rdrand_tmo, rdrand, &rdrand_tmo);
rdrand(&rdrand_tmo);
}
#ifdef CRYPTO
/*
* Also, if the chip has crypto available, enable it.
*/
if (amd64_has_xcrypt)
viac3_crypto_setup();
if (amd64_has_aesni)
aesni_setup();
#endif
}
void
cpu_configure(void)
{
splhigh();
softintr_init();
if (config_rootfound("mainbus", "mainbus") == 0)
panic("no mainbus found");
/* Configuration is finished, turn on interrupts. */
spl0();
cold = 0;
}
void
cpu_configure(void)
{
if (config_rootfound("mainbus", NULL) == NULL)
panic("mainbus not configured");
/*
* We're ready to start up. Clear CPU cold start flag.
* Soft cold-start flag will be cleared in configure().
*/
if (dep_call->cpu_clrf)
(*dep_call->cpu_clrf)();
}
void
cpu_configure(void)
{
splhigh();
splserial();
config_hook_init();
if (config_rootfound("mainbus", NULL) == NULL)
panic("no mainbus found");
/* Configuration is finished, turn on interrupts. */
spl0();
}
/*
* Determine device configuration for a machine.
*/
void
cpu_configure(void)
{
intr_init();
calc_delayconst();
/* Make sure that timers run at CPU frequency */
mtdcr(DCR_CPC0_CR1, mfdcr(DCR_CPC0_CR1) & ~CPC0_CR1_CETE);
if (config_rootfound("plb", NULL) == NULL)
panic("configure: mainbus not configured");
(void)spl0();
}
/*
* void cpu_configure()
*
* Configure all the root devices
* The root devices are expected to configure their own children
*/
void
cpu_configure(void)
{
struct mainbus_attach_args maa;
(void) splhigh();
(void) splserial(); /* XXX need an splextreme() */
maa.ma_name = "mainbus";
config_rootfound("mainbus", &maa);
/* Time to start taking interrupts so lets open the flood gates .... */
spl0();
}
/*
* Configure all devices on system
*/
void
cpu_configure(void)
{
intr_init();
/* Kick off autoconfiguration. */
if (config_rootfound("mainbus", NULL) == NULL)
panic("no mainbus found");
/*
* Hardware interrupts will be enabled in
* sys/arch/mips/mips/mips3_clockintr.c:mips3_initclocks()
* to avoid hardclock(9) by CPU INT5 before softclockintr is
* initialized in initclocks().
*/
}
