int cm3ice_run(cm3ice_ctrl_t * ctrl)
{
int ret;
DCC_LOG(LOG_INFO, ".");
if ((ret = core_resume(ctrl)) != ICE_OK) {
DCC_LOG(LOG_ERROR, "core_resume()");
}
return ret;
}
static void handle_reset(td243fc_rev2_softc_t *sc)
{
if (sc->is_suspend)
{
core_resume(sc->core_ctx);
sc->is_suspend = 0;
}
core_disconnect(sc->core_ctx);
sc->address = 0;
set_hw_address(sc);
sc->sys_intr_mask |= (TD243FC_SUSP | TD243FC_DONEREG);
WRITE4(TD243FC_SYSTEM_INT_ENABLE_REG, sc->sys_intr_mask);
/* Configure EP0 OUT for SETUP packet */
WRITE4(TD243FC_EPN_CONFIG_CONTROL_REG(0, 0),
BFSET4(TD243FC_FORMAT, TD243FC_CTRL_EP) |
BFSET4(TD243FC_MAXPKTSIZ, TD243FC_EP0_MAX_PACKET_SIZE));
WRITE4(TD243FC_EPN_XY_BUFFER_ADDRESS_REG(0,0),
BFSET4(TD243FC_XBSA, TD243FC_GET_IADDR(sc->ep[0].xaddr)) |
BFSET4(TD243FC_YBSA, TD243FC_GET_IADDR(sc->ep[0].yaddr)));
/* Configure EP0 IN */
WRITE4(TD243FC_EPN_CONFIG_CONTROL_REG(0, 1),
BFSET4(TD243FC_FORMAT, TD243FC_CTRL_EP) |
BFSET4(TD243FC_MAXPKTSIZ, TD243FC_EP0_MAX_PACKET_SIZE));
WRITE4(TD243FC_EPN_XY_BUFFER_ADDRESS_REG(0,1),
BFSET4(TD243FC_XBSA, TD243FC_GET_IADDR(sc->ep[1].xaddr)) |
BFSET4(TD243FC_YBSA, TD243FC_GET_IADDR(sc->ep[1].yaddr)));
/* Reset toggle for all endpoints */
WRITE4(TD243FC_EP_TOGGLE_REG, READ4(TD243FC_EP_TOGGLE_REG));
/* Enable EP0 */
ENABLE_EP(0, 0);
ENABLE_EP(0, 1);
WRITE4(TD243FC_EP_READY_REG, READ4(TD243FC_EP_READY_REG));
prepare_setup_transfer(sc);
}
static void dcd_soft_intr(void *arg)
{
td243fc_rev2_softc_t *sc = (td243fc_rev2_softc_t *)arg;
juint32_t sys_intr, ep_intr;
juint32_t fc_cmd;
DBG_V(DSLAVE_DCD, ("DCD: dcd_soft_intr\n"));
jspinlock_lock(sc->sc_lock);
{
sys_intr = sc->sys_intr;
ep_intr = sc->ep_intr;
fc_cmd = sc->fc_cmd;
sc->sys_intr = sc->ep_intr = sc->fc_cmd = 0;
}
jspinlock_unlock(sc->sc_lock);
sys_intr &= sc->sys_intr_mask;
ep_intr &= sc->ep_intr_mask;
/* Acknowledge the interuppts */
WRITE4(TD243FC_SYSTEM_INT_STATUS_REG, sys_intr);
/* HSU Addition */
/* Handle EP interrupts first. Fix for the case where OUT EP interrupt and
subsequent RESET interrupt are handled together. So the OUT EP interrupt
has to be handled first. The opposite case was not observed. */
if (sys_intr & TD243FC_DONEREG)
{
juint_t i;
sc->add_to_list = TRUE;
/* Handle interrupts on EP0 (IN and OUT interrupts) */
if (ep_intr & (TD243FC_EP_BIT(0, 0) | TD243FC_EP_BIT(0, 1)))
handle_ep0(sc, ep_intr);
/* Handle interrupts on endpoints other than EP0 */
for (i = 2; i < TD243FC_EP_NUM * 2; i++)
{
if (ep_intr & (1<<i))
handle_epn(sc, i);
}
/* Clear interrupts of handled EPs */
WRITE4(TD243FC_EP_DONE_STATUS_REG, ep_intr);
sc->add_to_list = FALSE;
if (sc->ep_ready)
{
WRITE4(TD243FC_EP_READY_REG, sc->ep_ready);
sc->ep_ready = 0;
}
}
/* HSU End */
if ((sys_intr & TD243FC_BUSRST) && (fc_cmd & TD243FC_RESETDET))
{
DBG_V(DSLAVE_DCD, ("DCD: Bus reset detected\n"));
handle_reset(sc);
/* Since we enable interrupts other then BUSRST only in handle_reset,
* no need to handle other interrupts together with BUSRST */
goto Exit;
}
if ((sys_intr & TD243FC_RESUME) && (fc_cmd & TD243FC_RSMINPROG))
{
if (sc->is_suspend)
{
DBG_V(DSLAVE_DCD, ("DCD: RESUME detected\n"));
core_resume(sc->core_ctx);
sc->is_suspend = 0;
sc->sys_intr_mask &= ~TD243FC_RESUME;
sc->sys_intr_mask |= TD243FC_SUSP;
WRITE4(TD243FC_SYSTEM_INT_ENABLE_REG, sc->sys_intr_mask);
}
}
if ((sys_intr & TD243FC_SUSP) && (fc_cmd & TD243FC_SUSPDET))
{
if (!sc->is_suspend)
{
DBG_V(DSLAVE_DCD, ("DCD: SUSPEND detected\n"));
core_suspend(sc->core_ctx);
sc->is_suspend = 1;
sc->sys_intr_mask &= ~TD243FC_SUSP;
sc->sys_intr_mask |= TD243FC_RESUME;
WRITE4(TD243FC_SYSTEM_INT_ENABLE_REG, sc->sys_intr_mask);
SET4(TD243FC_COMMAND_REG, TD243FC_SUSPDET);
}
}
/* HSU Addition */
/* Moved handling of TD243FC_DONEREG interrupt from here to the beginning
of the function */
/* HSU End */
WRITE4(TD243FC_SYSTEM_INT_ENABLE_REG, sc->sys_intr_mask);
Exit:
/* Ack & Enable device controller global interrupt */
SET4(TD243FC_CHIP_INT_ENABLE_REG, TD243FC_INTF);
DBG_V(DSLAVE_DCD, ("DCD: dcd_soft_intr finished\n\n\n"));
}